lithography
![Brian Piercy](data:image/svg+xml;utf8,<svg xmlns="http://www.w3.org/2000/svg" viewBox="0 0 24 24" fill="%230A66C2"><path d="M20.447 20.452H16.89v-5.569c0-1.328-.027-3.037-1.852-3.037-1.853 0-2.136 1.445-2.136 2.939v5.667H9.351V9h3.414v1.561h.046c.477-.9 1.637-1.85 3.37-1.85 3.601 0 4.267 2.37 4.267 5.455v6.286zM5.337 7.433a1.982 1.982 0 1 1 0-3.964 1.982 1.982 0 0 1 0 3.964zm1.782 13.019H3.555V9h3.564v11.452zM22.225 0H1.771C.792 0 0 .774 0 1.729v20.542C0 23.227.792 24 1.771 24h20.451C23.2 24 24 23.227 24 22.271V1.729C24 .774 23.2 0 22.222 0h.003z"/></svg>)
The AI era needs ever faster chips. ASML has a monopoly on the expensive contraptions needed to pattern them. Can anyone catch up?
file format used for specification of data structures for photomask production
This blog looks at the details of how Synopsys IC Validator can overcome the advanced node physical verification bottleneck.
Lace, a Norway-headquartered chipmaking equipment startup which is backed by Microsoft, has raised $40 million in funding to further develop a technology that could enable significant advances in semiconductor design and manufacturing, the company said on Monday.
Modeling, simulation, and digital twins enable EUV innovation.
The discussion of any particular lithographic application often refers to…
Faster masks, less power.
On how to reduce transistor capacitance at the 5nm node using a source/drain contact recess.
TSMC is moving to production with the NVIDIA cuLitho computational lithography platform to accelerate manufacturing of advanced semiconductor chips.