New Transistor Structures At 3nm/2nm
Gate-all-around FETs will replace finFETs, but the transition will be costly and difficult.
chip-design
Die Per Wafer (free) Calculator
How can you calculate the number of dies per wafer? A free online tool, DPW equation and reference to two other DPW calculators. Trusted by Amkor and GF.
The Ultimate Guide to Static Timing Analysis (STA)
Static Timing Analysis? Read here the best overview to STA, including theory, real examples, ilustrations, tips and tricks.
Introduction to Thermal Characterization Parameters
In this article, we’ll discuss another group of thermal data, called thermal characterization parameters denoted by the Greek letter Psi (Ψ).
Die Yield Calculator | iSine Analog, Digital & Mixed Signal IC Solutions
DIE YIELD CALCULATOR Use this online calculator to figure out die yield using Murphy’s model. You’ll need to know the die size, wafer diameter, and defect density. iSine is your complete resource for ASIC design – from concept to manufacturing and testing. We have expertise in…
Junction-to-Case Thermal Resistance in Thermal Design
Learn about an important thermal metric for designing the interface between an IC package and a heat sink.
Designing with a Heat Sink for Junction-to-Case Thermal Resistance
Watch the thermal measurement, junction-to-case thermal resistance, in action as we use it to calculate the thermal considerations for a given system.
10 basic advanced IC packaging terms to know
Engineers must keep pace with advanced IC packaging technology as it evolves rapidly, starting with understanding the basic terms.
How Junction-to-Ambient Thermal Resistance of an IC Package Affects Thermal
Assessing the thermal performance of an IC package becomes easier if you understand this common, but often misapplied, parameter known as theta JA.
Transistor Sizing in VLSI Design Using the Linear Delay Model - Technical A
In this article, we will learn how to find the optimal size of a transistor/logic gate present in a larger circuit to provide the desired performance using the linear delay model.
FinFETs Give Way to Gate-All-Around | Lam Research
When they were first commercialized at the 22 nm node, finFETs represented a revolutionary change to the way we build transistors, the tiny switches in the “brains” of a chip. As compared to...
The Elmore Delay Model in VLSI Design
In this article, we'll discuss the Elmore delay model, which provides a simplistic delay analysis that avoids time-consuming numerical integration/differential equations of an RC network.
Techniques to Reduce Timing Violations using Clock Tree Optimizations in Synopsys IC Compiler II - Semiwiki
The semiconductor industry growth is increasing exponentially with high speed…
Making Full Memory IP Robust During Design - Semiwiki
Looking at a typical SoC design today it's likely to…
Verification Of Multi-Cycle Paths And False Paths
Single-clock design is not always as easy as it seems.
Making SPICE available for everyone
SPICE (Simulation Program with Integrated Circuit Emphasis) is an open-source analog electronic circuit simulator. | SPICE is undoubtedly one of the most popular modeling libraries available, and Japanese e-commerce company MoDeCH is seeking to make the power of SPICE available…
CMOS Circuit Design, Layout, and Simulation
Five Rules For Correlating Rule-based And Field Solver Parasitic Extraction
Accurately determine parasitic effects with the proper set up of two different methods.
Process Corner Explosion
Process Corner Explosion, At 7nm and below, modeling what will actually show up in silicon is a lot more complicated.
gplEDA Homepage
lect04_LEF.pdf
Comparing NLDM And CCS delay models - Paripath - improving sign-off
Post date: Sep 19, 2014 10:01:08 PM
Bsim3
Clash of the Foundries: Gate All Around + Backside Power at 2nm
Fab Cost, WFE Implications, Backside Power Details