Clock Gating is defined as: “Clock gating is a technique/methodology to turn off the clock to certain parts of the digital design when not needed”. The Need for Clock Gating With most of the SoCs heavily constrained by power budgets, it is of utmost importance to reduce power…
Leakage current can contribute to power dissipation, especially at lower threshold voltages. Learn about six types of leakage current that can be found in MOS transistors.
Gate-all-around FETs will replace finFETs, but the transition will be costly and difficult.
How can you calculate the number of dies per wafer? A free online tool, DPW equation and reference to two other DPW calculators. Trusted by Amkor and GF.
Static Timing Analysis? Read here the best overview to STA, including theory, real examples, ilustrations, tips and tricks.
In this article, we’ll discuss another group of thermal data, called thermal characterization parameters denoted by the Greek letter Psi (Ψ).
DIE YIELD CALCULATOR Use this online calculator to figure out die yield using Murphy’s model. You’ll need to know the die size, wafer diameter, and defect density. iSine is your complete resource for ASIC design – from concept to manufacturing and testing. We have expertise in…
Learn about an important thermal metric for designing the interface between an IC package and a heat sink.
Watch the thermal measurement, junction-to-case thermal resistance, in action as we use it to calculate the thermal considerations for a given system.
Engineers must keep pace with advanced IC packaging technology as it evolves rapidly, starting with understanding the basic terms.
Assessing the thermal performance of an IC package becomes easier if you understand this common, but often misapplied, parameter known as theta JA.
In this article, we will learn how to find the optimal size of a transistor/logic gate present in a larger circuit to provide the desired performance using the linear delay model.
When they were first commercialized at the 22 nm node, finFETs represented a revolutionary change to the way we build transistors, the tiny switches in the “brains” of a chip. As compared to...
In this article, we'll discuss the Elmore delay model, which provides a simplistic delay analysis that avoids time-consuming numerical integration/differential equations of an RC network.
The semiconductor industry growth is increasing exponentially with high speed…
Looking at a typical SoC design today it's likely to…
Single-clock design is not always as easy as it seems.
SPICE (Simulation Program with Integrated Circuit Emphasis) is an open-source analog electronic circuit simulator. | SPICE is undoubtedly one of the most popular modeling libraries available, and Japanese e-commerce company MoDeCH is seeking to make the power of SPICE available…
Accurately determine parasitic effects with the proper set up of two different methods.
Process Corner Explosion, At 7nm and below, modeling what will actually show up in silicon is a lot more complicated.
Post date: Sep 19, 2014 10:01:08 PM
Fab Cost, WFE Implications, Backside Power Details