An Introduction to Using Logic Gates in LTspice
This article explains how to successfully integrate logic gates into an LTspice simulation.
chip-design
Simulating MOSFET Current-Voltage Characteristics Using Advanced SPICE Mode
In this article, we use a SPICE model for 90 nm CMOS to plot key electrical relationships of an NMOS transistor.
Using Advanced SPICE models to Characterize an NMOS Transistor
SPICE models designed for specific CMOS process nodes can enhance simulations of integrated-circuit transistors. Learn where to find these models and how to use them.
SystemVerilog: Ultimate Guide
In the realm of hardware design and verification, SystemVerilog stands as a titan among languages, beckoning engineers and developers with its robust capabilities. Originating from the fusion of Verilog with hardware verification languages, SystemVerilog’s evolution has…
Competitive Open-Source EDA Tools
A technical paper titled “Basilisk: Achieving Competitive Performance with Open EDA Tools on an Open-Source Linux-Capable RISC-V SoC” was published by researchers at ETH Zurich and University of Bologna. Abstract: “We introduce Basilisk, an optimized application-specific…
HiFi-DRAM: Enabling High-fidelity DRAM Research by Uncovering Sense Amplifi
DRAM research is difficult. Work that aims to be applicable to commodity devices should consider the sense amplifier internal layouts, transistor dimensions and circuit typologies used by real devices. These are all essential elements that must be considered while proposing new…
A Comprehensive RF Characterization and Modeling Methodology for the 5nm Te
This paper aims to provide insights into the thermal, analog, and RF attributes, as well as a novel modeling methodology, for the FinFET at the industry standard 5nm CMOS technology node. Thermal characterization shows that for a 165K change in temperature, the Sub-threshold…
The Ultimate Signoff (TapeOut) Checklist
In semiconductor design, “sign-off” during the tape-out (tapeout) of a chip refers to the formal approval process to ensure that the chip design is error-free, meets all specifications, and is ready for manufacturing at the foundry. It is essential because it minimizes the risk…
VLSI Physical Design
Criteria & Assumptions — SkyWater SKY130 PDK 0.0.0-356-g49d3c73 documentati
The Future of the Transistor
Planar to FinFET to Nanosheet to Complementary FET to 2D
Ending an Ugly Chapter in Chip Design
Study tries to settle a bitter disagreement over Google’s chip design AI
True 3D Is Much Tougher Than 2.5D
While terms often are used interchangeably, they are very different technologies with different challenges.
RDL and Flip Chip Design
RDL, an abbreviation for Redistribution Layer, that is, to make one or more layers of metal on the active chip side to redistribute the pins of the chip.
The Most Complex Chip Ever Made?
Historically Intel put all its cumulative chip knowledge to work advancing Moore's Law and applying those learnings to its future CPUs. Today, some of
Video: Intel EMIB Technology Explained
Intel's multi-die interconnect bridge (EMIB) is an approach to in-package high-density interconnect of heterogeneous chips.
US Semiconductor Manufacturing | CHIPS and Science Act | Intel®
Powered by the promises of the CHIPS Act, Intel is investing more than $100 billion to increase domestic chip manufacturing capacity and capabilities.
Tiny Tapeout - Tiny Tapeout
From idea to chip design in minutes! TT09 Closes in TT09 Closes in 44 DAYS 44 HOURS 44 MINS 44 SECS Tiles PCBs Tiny Tapeout is an educational project that makes it easier and cheaper than ever to get your designs manufactured on a real chip! Read the paper here. See what other…
Asynchronously Parallel Optimization Method For Sizing Analog Transistors U
A new technical paper titled “APOSTLE: Asynchronously Parallel Optimization for Sizing Analog Transistors Using DNN Learning” was published by researchers at UT Austin and Analog Devices. Abstract “Analog circuit sizing is a high-cost process in terms of the manual effort…
thejackal360/OpenSPICE: Simulate electronic circuit using Python and the Ngspice / Xyce simulators
Simulate electronic circuit using Python and the Ngspice / Xyce simulators - thejackal360/OpenSPICE
Improve Signal Integrity by Reducing PCB Trace Impedance Variation
Achieving better signal integrity in a PCB design can be a challenge. Learn how PCB trace impedance variation plays a role, and how advanced tools can help smooth the way.
An AI 'Engineer' Has Now Designed 100 Chips - ExtremeTech
AI firm Synopsys has announced that its DSO.ai tool has successfully aided in the design of 100 chips, and it expects that upward trend to continue.
bmurmann/Book-on-MOS-stages: Book repository "Analysis and Design of Elementary MOS Amplifier Stages"
Book repository "Analysis and Design of Elementary MOS Amplifier Stages" - bmurmann/Book-on-MOS-stages
My Articles on AAC (Page I)
The following is a list of my articles on various topics. Besides technical articles, news pieces that might have useful technical information are also included. You can find my articles on FPGA...
The Inner Beauty of Basic Electronics
Open Circuits: The Inner Beauty of Electronics is a visual feast for those who love electronics.
RF Design Basics—Introduction to Transmission Lines
Learn about voltage waves and how they relate to an important basic concept of radio frequency (RF) circuit design: transmission lines.
Inside the 8086 processor's instruction prefetch circuitry
The groundbreaking 8086 microprocessor was introduced by Intel in 1978 and led to the x86 architecture that still dominates desktop and se...
Big Trouble in Little Interconnects
Interconnects—those sometimes nanometers-wide metal wires that link transistors into circuits on an IC—are in need of a major overhaul. And as chip fabs march toward the outer reaches of Moore’s Law, interconnects are also becoming the industry’s choke point.
Book-on-MOS-stages/Analysis and Design of Elementary MOS Amplifier Stages.p
Book repository "Analysis and Design of Elementary MOS Amplifier Stages" - bmurmann/Book-on-MOS-stages
Ultimate Guide: Clock Tree Synthesis
A vast majority of modern digital integrated circuits are synchronous designs. They rely on storage elements called registers or flip-flops, all of which change their stored data in a lockstep manner with respect to a control signal called the clock. In many ways, the clock…
Performance Benefits of Using Huge Pages for Code. | Easyperf
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High-Performance 5G IC Designs Need High-Performance Parasitic Extraction
The high frequencies and data rates involved in 5G designs makes layout verification all the more important.
Designing and Simulating Low-Voltage CMOS Circuits Using Four-Parameter Mod
New technical paper titled “Bridging the Gap between Design and Simulation of Low-Voltage CMOS Circuits” from researchers at Federal University of Santa Catarina, Brazil. Abstract “This work proposes a truly compact MOSFET model that contains only four parameters to assist an…
Thermal Management Challenges and Requirements of 3 types of Microelectroni
New technical paper titled “A Review on Transient Thermal Management of Electronic Devices” from researchers at Indian Institute of Technology Bombay. Abstract “Much effort in the area of electronics thermal management has focused on developing cooling solutions that cater to…
Another Firing Among Google’s A.I. Brain Trust, and More Discord (Published 2022)
The researchers are considered a key to the company’s future. But they have had a hard time shaking infighting and controversy over a variety of issues.
The X-Ray Tech That Reveals Chip Designs
When you’re baking a cake, it’s hard to know when the inside is in the state you want it to be. The same is true—with much higher stakes—for microelectronic chips: How can engineers confirm that what’s inside has truly met the intent of the designers? How can a semiconductor…
HewlettPackard/cacti: An integrated cache and memory access time, cycle time, area, leakage, and dynamic power model
An integrated cache and memory access time, cycle time, area, leakage, and dynamic power model - HewlettPackard/cacti
How to Simulate a Phase-Locked Loop - Technical Articles
This article presents an LTspice circuit that can be used to explore the behavior of a phase-locked loop.
How to make multicore chips faster more efficient
Magic VLSI
Magic VLSI: Resource Page
OpenROAD – Home
Library Design - Silvaco
Silvaco provides standard cell library design and optimization services
Effect of Design on Transistor Density - Semiwiki
I have written a lot of articles looking at leading…
Understanding SoC Clock Design - AnySilicon
SoC clock tree overview, metrics that help qualify a clock tree and most commonly used clock tree distribution methodologies.
Category:EDA file formats
File formats used by EDA tools.
Impact Of GAA Transistors At 3/2nm
Some things will get better from a design perspective, while others will be worse.
Bumps Vs. Hybrid Bonding For Advanced Packaging
New interconnects offer speed improvements, but tradeoffs include higher cost, complexity, and new manufacturing challenges.
The Ultimate Guide to Clock Gating
Clock Gating is defined as: “Clock gating is a technique/methodology to turn off the clock to certain parts of the digital design when not needed”. The Need for Clock Gating With most of the SoCs heavily constrained by power budgets, it is of utmost importance to reduce power…
6 Causes of MOS Transistor Leakage Current
Leakage current can contribute to power dissipation, especially at lower threshold voltages. Learn about six types of leakage current that can be found in MOS transistors.