Analyzing Nvidia GB10's GPU
Looking at Nvidia's latest effort to make a big iGPU
chip-design
Designing AI Chip Software and Hardware
Designing AI Chip Hardware and Software Bjarke Hammersholt Roune 2026 This document is, for now, open for comments. You can use the Google Docs comment feature to add comments anywhere. Thanks! What is this document? I was going to start an AI chip company and this document…
Taalas is replacing programmable GPUs with hardwired AI chips to achieve 17,000 tokens per second for ubiquitous inference - MarkTechPost
Bulk RRAM: Scaling the AI Memory Wall
UC San Diego researchers have reimagined RRAM, creating a device that could redefine AI's memory challenges. Discover how this could impact edge computing.
Gate-All-Around (GAA) Technology for Sustainable AI - SemiWiki
Key takeaways ▼ The transition from FinFET to Gate-All-Around (GAA) transistor technology represents a pivotal moment in the evolution of logic devices, driven by both physical scaling limits and the … Continue reading "Gate-All-Around (GAA) Technology for Sustainable AI"
Understanding the PDK Generation Process - Technical Articles
In this article, we'll walk through the steps of generating a Process Design Kit (PDK) for digital standard cell libraries.
Impact Of On-Chip SRAM Size And Frequency On Energy Efficiency And Performance of LLM Inference (Uppsala Univ.)
A new technical paper titled “Prefill vs. Decode Bottlenecks: SRAM-Frequency Tradeoffs and the Memory-Bandwidth Ceiling” was published by researchers at Uppsala University. Abstract “Energy consumption dictates the cost and environmental impact of deploying Large Language…
Our simulation methodology combines OpenRAM for energy modeling, LLMCompass for latency simulation, and ScaleSIM for systolic array operational intensity.
Counter-intuitively, high compute frequency can reduce total energy by reducing execution time and consequently decreasing static energy consumption more than the resulting dynamic power increase
Solving The Problems of HBM-on-Logic
Future AI Accelerators Might Need To Be Slower To Be Faster
This means a singular high-powered compute die consuming ~400W, with multiple 12-Hi HBM stacks.
peak GPU temperature of 69.1ºC, with the HBM silicon reaching around 60ºC in its worst case.
FPGAs Need a New Future
FPGAs are limited by outdated proprietary software. Learn how embracing open-source tools is necessary to modernize FPGA development and unlock their full potential.
Unusual circuits in the Intel 386's standard cell logic
I've been studying the standard cell circuitry in the Intel 386 processor recently. The 386, introduced in 1985, was Intel's most complex pr...
Why In-Memory Computation Is So Important For Edge AI
Researchers focus on limiting data movement to reduce power and latency in edge devices.
AMD’s Chiplet APU: An Overview of Strix Halo
Hello you fine Internet folks!
Interconnect Innovations In High Bandwidth Memory: Part 2
Bump technologies are being pushed beyond what was thought to be their physical and performance limits.
Beyond Von Neumann: Toward a unified deterministic architecture
The mechanism behind this is a time-resource matrix: A scheduling framework that orchestrates compute, memory and control resources across time. Much like a train timetable, scalar, vector and matrix operations move across a synchronized compute fabric without pipeline stalls or contention.
By predicting exactly when data will arrive — whether in 10 cycles or 200 — Deterministic Execution can slot dependent instructions into the right future cycle. This turns latency from a hazard into a schedulable event, keeping the execution units fully utilized and avoiding the massive thread and…
The Motorola 68000: A 32-Bit Brain in a 16-Bit Body
Motorola’s 68000 blended 32-bit power with a 16-bit bus, creating a balanced, orthogonal, and elegant architecture that powered everything from Macintosh to arcade machines.
The Demise Of Static Timing Verification?
Timing is increasingly dependent on vectors. Can static techniques continue to deliver the necessary results? Maybe.
3D-Stacked HBM Architecture Susceptibility To Thermal Attacks (NC A&T State, New Mexico State)
A new technical paper titled “On the Thermal Vulnerability of 3D-Stacked High-Bandwidth Memory Architectures” was published by researchers at North Carolina A&T State University and New Mexico State University. Abstract “3D-stacked High Bandwidth Memory (HBM) architectures…
Static Timing Analysis Signoff A comprehensive and Robust Approach
By Zameer Mohammed Once a chip is taped out, changes in design are not possible – Silicon is unforgiving, does not allow postproduction modifications. In contrast, software can be updated … Continue reading "Static Timing Analysis Signoff A comprehensive and Robust Approach"
Backside Power Delivery (BSPD) Wiki
Backside Power Delivery (BSPD), also called Backside Power Delivery Network (BSPDN) or backside power via (BPV) technology, is a semiconductor manufacturing innovation in which the chip’s primary power distribution network … Continue reading "Backside Power Delivery (BSPD) Wiki"
Rapidus’ 2nm “2HP” Process Will Reportedly Compete With TSMC’s N2 in Logic Density, Also Beating Intel’s…
Rapidus is advancing with its 2nm process. For the first time, the node's logic density has been reported, and it's on par with TSMC.
BSPDN, Intel occupies some of the front-side metal layers, which is why there's a drop in the density figure
Here be dragons: Preventing static damage, latchup, and metastability in the 386
I've been reverse-engineering the Intel 386 processor (from 1985), and I've come across some interesting circuits for the chip's input/outpu...
RDNA 4's "Out-of-Order" Memory Accesses
Examining RDNA 4's out-of-order memory accesses in detail, and investigating with testing
How to reverse engineer an analog chip: the TDA7000 FM radio receiver
Have you ever wanted to reverse engineer an analog chip from a die photo? Wanted to understand what's inside the "black box" of an integrate...
Rethinking Scan Chains In Semiconductor Test
Finding defects now requires multiple data types, and a much more thorough search.
Prototype Computer Uses Noise to Its Advantage
Thermodynamic computing isn't just a rebrand of probabilistic computing
Normal Computing’s prototype chip, which they termed the stochastic processing unit (SPU), consists of eight capacitor-inductor resonators and random noise generators. Each resonator is connected to each other resonator via a tunable coupler. The resonators are initialized with randomly generated…
Metal fill extraction: Breaking the speed-accuracy tradeoff
An adaptive metal fill extraction technique dynamically adjusts the level of detail based on the design context, such as the density of...
Die-to-die Interconnect Standards In Flux
Many features of UCIe 2.0 seen as “heavy” are optional, causing confusion.
The spec is defined with so many variants that you can tailor it to your exact needs. It’s applicable for everything from automotive to high-performance compute to AI to mil/aero because it has so many flavors. That’s also a curse to an IP provider. How do you support all those flavors?”
the latter predominates, since virtually all projects underway are internal projects, with all chiplets being internally created and applied. Interoperability with externally sourced chiplets is therefore not a concern
Performance Analysis and Tuning on Modern CPUs
Notes on the Pentium's microcode circuitry
Most people think of machine instructions as the fundamental steps that a computer performs. However, many processors have another layer of ...
First-Time Silicon Success Plummets
Number of designs that are late increases. Rapidly rising complexity is the leading cause, but tools, training, and workflows need to improve.
“Historically, it’s been around 30%. Two years ago it dropped to 24% from 2023 to 2024. It dropped to 14% this time around. That’s one data point. Another is that historically we’ve seen about two-thirds of projects were behind schedule. That increased to 75% behind schedule.”
AMD's Strix Halo - Under the Hood
Hello you fine Internet folks,
The Pentium contains a complicated circuit to multiply by three
In 1993, Intel released the high-performance Pentium processor, the start of the long-running Pentium line. I've been examining the Pentium'...
100x Defect Tolerance: How Cerebras Solved the Yield Problem - Cerebras
[vc_row][vc_column column_width_percent=”90″ gutter_size=”3″ overlay_alpha=”50″ shift_x=”0″ shift_y=”0″ shift_y_down=”0″ z_index=”0″ medium_width=”0″ mobile_width=”0″ width=”1/1″ uncode_shortcode_id=”158708″][vc_column_text uncode_shortcode_id=”154284″] Conventional wisdom in…
AMD Reveals Real Reason It Won't Put 3D V-Cache On Multiple CCDs
After persistent rumors refused to recede, AMD steps in with a clear explanation why dual-CCD V-Cache doesn't exist.
No, the actual reason AMD won't make a dual-V-Cache chip is much simpler: it would be pointless and a waste of money.
Pi in the Pentium: reverse-engineering the constants in its floating-point unit
Intel released the powerful Pentium processor in 1993, establishing a long-running brand of high-performance processors. 1 The Pentium incl...
Note: Based on Ken Shirriff's article "[Pi in the Pentium: reverse-engineering the constants in its floating-point unit](https://www.righto.com/2025/01/pentium-floating-point-ROM.html)", here is an outline of each section with explanations of the findings: | Section | Findings | |---|---| | **Introduction** | The Pentium processor's floating-point unit (FPU) computes transcendental functions like sine…
CMU Researchers Introduce TNNGen: An AI Framework that Automates Design of Temporal Neural Networks (TNNs) from PyTorch Software Models to…
Designing neuromorphic sensory processing units (NSPUs) based on Temporal Neural Networks (TNNs) is a highly challenging task due to the reliance on manual, labor-intensive hardware development processes. TNNs have been identified as highly promising for real-time edge AI…
Intel's $475 million error: the silicon behind the Pentium division bug
In 1993, Intel released the high-performance Pentium processor, the start of the long-running Pentium line. The Pentium had many improvement...
Slim-Llama: An Energy-Efficient LLM ASIC Processor Supporting 3-Billion Parameters at Just 4.69mW
Large Language Models (LLMs) have become a cornerstone of artificial intelligence, driving advancements in natural language processing and decision-making tasks. However, their extensive power demands, resulting from high computational overhead and frequent external memory…
AMD Disables Zen 4's Loop Buffer
A loop buffer sits at a CPU's frontend, where it holds a small number of previously fetched instructions.
Predictive PDK (ASAP) – ASU Engineering
Antenna diodes in the Pentium processor
I was studying the silicon die of the Pentium processor and noticed some puzzling structures where signal lines were connected to the silico...
Signal Integrity Basics
eBook: Pre-requisites for successful high-performance electronic system design.
Report: Intel Meteor Lake In Short Supply Due to Yield Issues, Intel Runnin
Surveying the Landscape of Smartphone Processors
There are many chip partitioning and placement tradeoffs when comparing top-tier smartphone processor designs.
Understanding Two Port Amplifier Power Gains
Transducer, Unilateral, Available and Power Gain; what they mean and how to calculate them.
ABCs of Power Amplifier Classes: Foundations
Basic concepts required to understand classes of operation in power amplifiers.
Introduction to the Common-Drain Amplifier: Large-Signal Behavior
Also known as the source follower, the common-drain amplifier is notable for its low output impedance. This article introduces the basic common-drain configuration and examines its large-signal characteristics.
Zen 5’s 2-Ahead Branch Predictor Unit: How a 30 Year Old Idea Allows for Ne
When I recently interviewed Mike Clark, he told me, “…you’ll see the actual foundational lift play out in the future on Zen 6, even though it was really Zen 5 that set the table for that.” And at that same Zen 5 architecture event, AMD’s Chief Technology Officer Mark Papermaster…
efabless.com
Chip Creation Made Simple
Standard cells: Looking at individual gates in the Pentium processor
Intel released the powerful Pentium processor in 1993, a chip to "separate the really power-hungry folks from ordinary mortals." The origin...