How Agentic AI Chip Design Built a Full RISC-V Core

Startup Verkor.io’s agentic AI orchestrated the entire design process from a 219-word prompt

RISC-V In The Datacenter Is No Risky Proposition

It was only a matter of time, perhaps, but the skyrocketing costs of designing chips is colliding with the ever-increasing need for performance,

SweRV - An Annotated Deep Dive

openhwgroup/cva6: The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux - openhwgroup/cva6

RISC-V from scratch 1: Introduction, toolchain setup, and hello world!

A post that discusses what RISC-V is and why it’s important, teaches readers how to install the GNU RISC-V toolchain, and walks through building and running a simple C program on emulated RISC-V hardware.

RISC-V from scratch 2: Hardware layouts, linker scripts, and C runtimes

A post describing how C programs get to the main function. Devicetree layouts, linker scripts, minimal C runtimes, GDB and QEMU, basic RISC-V assembly, and other topics are reviewed along the way.