In 1980, Intel introduced the 8087, a chip that made floating-point operations much faster in the IBM PC and other systems. Although the 808...
1648 micro-instructions
floating-point calculations on 80-bit values
Chinese memory chip manufacturer CXMT's recent claim that it would 'leapfrog' established memory giants Samsung, SK hynix and Micron by two years is nothing but that of a paper tiger, analysts from Rosenblatt believe. CXMT's President, Dr. Cao Kanyu, recently claimed at the…
Note: Standard designs, which are referred to as 6F², have transistors, also referred to as pillars, staggered in an offset grid pattern between the bit and word lines. On the other hand, 4F² optimizes the design by placing the pillars over the interesting bit and word lines to reduce the area of the memory cell. The reason 4F² is able to reduce the area is through vertically stacking the bit line…
Standard designs, which are referred to as 6F², have transistors, also referred to as pillars, staggered in an offset grid pattern between the bit and word lines. On the other hand, 4F² optimizes the design by placing the pillars over the interesting bit and word lines to reduce the area of the…
The reason 4F² is able to reduce the area is through vertically stacking the bit line contacts, capacitors and transistors which are otherwise laid out horizontally in a 6F² cell design.
Complementary FETs (CFETs) extend nanosheet FET (NSFET) scaling by vertically stacking n- and p-type gate-all-around (GAA) devices, thereby shrinking standard-cell area. The performance gain, however, cannot be assessed from device metrics alone, as CFET layouts also introduce…
Note: Summary: This arXiv paper compares two next-generation chip technologies — A7 CFET and A10 NSFET — using a physics-based evaluation flow spanning from cell parasitics up to full-chip reliability. Approach: CFETs stack n- and p-type devices vertically to shrink cell area, but add extra cell-level resistance and capacitance. The authors built a flow linking calibrated device models, standard-cell…
Today’s tidal wave of queries is forcing hardware makers to pivot
Note: ### The AI Inference Revolution Is Here [IEEE Spectrum article](#rid:1854764141) — a survey of how the shift from AI training to AI **inference** is reshaping chip and memory design. **The shift** Since 2020, the AI story was about training ever-bigger models. In 2026 the spotlight has moved to inference — putting trained models to work. People actually use LLMs now, reasoning models run…
AI drastically shortened its design time; it will only get faster
How design-aware monitor analytics connects production measurements with device behavior and pre-silicon expectations.
The $9.45 billion global design IP budget is distributed across 12 distinct sub-categories, heavily dominated by two primary pillars: CPU...
A leaked Apple A20 Pro die shot reveals a record GPU core count for upgraded graphics, while new WMCM packaging unlocks a wider 96-bit memory bus width
d-Matrix is tackling the 3D DRAM heat problem by stacking memory beneath the XPU, but atomic-level flatness remains a brutal barrier.
Researchers have created a tiny chip that produces a stable “rainbow” of light capable of generating multiple high-frequency signals at once, potentially boosting the speed and capacity of future 6G networks. Its extreme precision could also make it valuable for quantum timing…
CXL memory expansion, with a side of compute
The company's ideas aren't novel, but it has solved long-standing challenges with 3D DRAM technology.
d-Matrix's Raptor 3D DRAM delivers 100 TB/s bandwidth at 0.37 pJ/bit, offering a high-efficiency alternative to SRAM and HBM for AI workloads
A look at AI Chip Architectures. NVIDIA, AMD, TPUs, Trainium, Groq, Cerebras.
Designing a semiconductor chip is not only about making it perform its intended function.
The most expensive part of HBM is not the DRAM. It is the piece of silicon underneath it. HBM moves data over a very wide parallel bus, roughly 1024 bits per stack. Every one of those wires has to be routed through a silicon interposer sitting between the memory and the compute…
Fundamentals of SRAM and how SRAM constraints affect array size scaling and LLM inference performance
When D-Wave bought Quantum Circuits for $550 million in the early days of this year, it marked a sig ...
Early tech demos show model-specific integrated circuits churning out up to 17,000 tokens a second
Arm’s 5-series cores are meant for tasks where performance barely matters, but power and area efficiency are top priorities.
Learn digital hardware design in the browser: write VHDL, Verilog and SystemVerilog, run real simulations, read waveforms, and see your RTL synthesized to a netlist. The skills behind FPGA and ASIC design, no installation required.
Cadence has announced that its AI-driven digital and custom reference flows, tools, and solutions are now Intel 18A-P & 14A certified.
A sample of the designs that followed Google's first Tensor Processing Unit.
How transmission line effects and power-supply induced jitter make high-speed HBM interconnect scaling one of the most challenging co-design issues in AI racks
tensordyne just announced their chip specs. their trick is to turn every multiply into an add using logarithms, a trick from 1962 that everyone tried and gave up on. here's the breakdown: the idea is simple. log(a×b) = log(a) + log(b). store your numbers as logs and every…
Read this blog to learn what PCI Express is, how PCIe 7.0 improves bandwidth and efficiency, and how features like PAM4, FEC, FLIT mode and AXI support next-generation AI, cloud, HPC and edge systems.
Note: RF design?
Freed from intelligibility and aesthetics, AI designs faster
It has been nine years since a Chinese HPC supercomputer was at the top of the High Performance Linp ...
Key physics constraints and architecture challenges for scaling data rates in DWDM - ring modulator physics, clocking, CW-DFB Laser, and package integration
Library of open source PDKs
NASA's High Performance Spaceflight Computing project aims to significantly enhance the computational capabilities of spacecraft, enabling autonomous operations and faster
How signal integrity influences complexity of modern wireline transceiver architecture from first principles
Learning from a classic AI accelerator - Eyeriss
How high-speed data requirements influence chip architectural complexity
Is Intel's EMIB better than TSMC's CoWoS for AI accelerators? A primer on both, an honest look at the trade-offs, and where it goes from here.
Laying the Groundwork of the Current Chip Design Paradigm
file format used for specification of data structures for photomask production
Q&A with SiTime CEO Rajesh Vashist
Tribal knowledge of RF design, EV range vs. temperature on the dyno, OpenAI's expanding robotic division, and more.
Disaggregated inference started as a software technique for splitting prefill and decode onto separate GPU pools. NVIDIA, Groq, Cerebras, and AWS are now taking it further with chips purpose-built for each phase.
prefill-decode disaggregation
production LLM serving
HBM, GDDR, and SRAM compared: how memory hierarchy, bandwidth, and capacity determine AI accelerator performance, cost, and which workloads each chip can serve.
prefill (processing the prompt), which is often compute-bound
decode (token-by-token generation), which is usually memory-bound
Sparse computing enables leaner, faster AI
Samsung has reportedly produced the world's first standalone DRAM module that uses a process tech below 10nm.
Note: The “1x, 1y, 1z, 1a…” naming is just the DRAM industry’s generational shorthand — each step is a shrink within the broad “10nm-class” umbrella, not a distinct architecture change. The progression: |Gen|Approx. node|Era | |---|------------|---------------------------| |1x |~18–19nm |~[2016–2017](tel:2016-2017)| |1y |~17nm |~2018 | |1z |~15–16nm |~[2019–2020](tel:2019-2020)| |1a |~14nm |~2021 | |1b…
Startup Verkor.io’s agentic AI orchestrated the entire design process from a 219-word prompt
This blog looks at the details of how Synopsys IC Validator can overcome the advanced node physical verification bottleneck.
The cost case is strengthening, but glass, warpage, and bonding yield stand in the way.