System-Technology Co-Evaluation of A7 CFET and A10 NSFET...

Complementary FETs (CFETs) extend nanosheet FET (NSFET) scaling by vertically stacking n- and p-type gate-all-around (GAA) devices, thereby shrinking standard-cell area. The performance gain, however, cannot be assessed from device metrics alone, as CFET layouts also introduce…

Note: Summary: This arXiv paper compares two next-generation chip technologies — A7 CFET and A10 NSFET — using a physics-based evaluation flow spanning from cell parasitics up to full-chip reliability. Approach: CFETs stack n- and p-type devices vertically to shrink cell area, but add extra cell-level resistance and capacitance. The authors built a flow linking calibrated device models, standard-cell…

The AI Inference Revolution Is Here

Today’s tidal wave of queries is forcing hardware makers to pivot

Note: ### The AI Inference Revolution Is Here [IEEE Spectrum article](#rid:1854764141) — a survey of how the shift from AI training to AI **inference** is reshaping chip and memory design. **The shift** Since 2020, the AI story was about training ever-bigger models. In 2026 the spotlight has moved to inference — putting trained models to work. People actually use LLMs now, reasoning models run…

Jalapeño Shows Power of LLMs for Chip Design

AI drastically shortened its design time; it will only get faster

Beyond Conventional Ring Oscillators: Purpose-Built Process Detectors For Deeper Silicon Insight

How design-aware monitor analytics connects production measurements with device behavior and pre-silicon expectations.

YosysHQ Yosys documentation

Reverse Engineering a Chip (or well, a GDS)

The $9.5 Billion Design IP Market: Shifting Boundaries, Arm’s Monopoly, and the RISC-V Response

The $9.45 billion global design IP budget is distributed across 12 distinct sub-categories, heavily dominated by two primary pillars: CPU...

Apple’s A20 Pro Front Side Die Shot Shows New Record For GPU Core Count To Deliver Better Graphics Performance, New Packaging Allows For…

A leaked Apple A20 Pro die shot reveals a record GPU core count for upgraded graphics, while new WMCM packaging unlocks a wider 96-bit memory bus width

AMD Says A Hybrid-Bonded 3D DRAM Is 17x More Energy Efficient Than An HBM Stack That Relies On Microbumps, But Thermal Hurdles Block…

d-Matrix is tackling the 3D DRAM heat problem by stacking memory beneath the XPU, but atomic-level flatness remains a brutal barrier.

A tiny “rainbow on a chip” could help supercharge 6G networks

Researchers have created a tiny chip that produces a stable “rainbow” of light capable of generating multiple high-frequency signals at once, potentially boosting the speed and capacity of future 6G networks. Its extreme precision could also make it valuable for quantum timing…

Hot Chips 2026: XCENA and Samsung’s Near-Memory Compute CXL Device

CXL memory expansion, with a side of compute

d-Matrix Claims 20x Bandwidth Density Over NVIDIA Rubin In New Chip

The company's ideas aren't novel, but it has solved long-standing challenges with 3D DRAM technology.

d-Matrix’s Raptor 3D DRAM Achieves SRAM-Class Bandwidth at 1/10th the HBM Power by Dropping PHY & Fusing DRAM Beneath the Compute

d-Matrix's Raptor 3D DRAM delivers 100 TB/s bandwidth at 0.37 pJ/bit, offering a high-efficiency alternative to SRAM and HBM for AI workloads

AI Chip Architectures

A look at AI Chip Architectures. NVIDIA, AMD, TPUs, Trainium, Groq, Cerebras.

Design for Testability (DFT): How Do We Know a Chip Actually Works?

Designing a semiconductor chip is not only about making it perform its intended function.

#semiconductor #hbm #chiplets #ucie | Paul Chao

The most expensive part of HBM is not the DRAM. It is the piece of silicon underneath it. HBM moves data over a very wide parallel bus, roughly 1024 bits per stack. Every one of those wires has to be routed through a silicon interposer sitting between the memory and the compute…

A Deep Dive into SRAM: The Staging Ground of LLM Inference

Fundamentals of SRAM and how SRAM constraints affect array size scaling and LLM inference performance

D-Wave Intros Two-Qubit, Error Correcting Gate For Its Dual-Rail Quantum Architecture

When D-Wave bought Quantum Circuits for $550 million in the early days of this year, it marked a sig ...

AMD acquires AI chip startup Taalas to boost inference performance by etching models into silicon

Early tech demos show model-specific integrated circuits churning out up to 17,000 tokens a second

Arm’s Cortex A55

Arm’s 5-series cores are meant for tasks where performance barely matters, but power and area efficiency are top priorities.

RisingEdge.pro | Learn Hardware Design Interactively

Learn digital hardware design in the browser: write VHDL, Verilog and SystemVerilog, run real simulations, read waveforms, and see your RTL synthesized to a netlist. The skills behind FPGA and ASIC design, no installation required.

Intel 18A-P and 14A gain Cadence’s full EDA toolchain, tightening the ecosystem push to challenge TSMC’s foundry lead

Cadence has announced that its AI-driven digital and custom reference flows, tools, and solutions are now Intel 18A-P & 14A certified.

AI Accelerators: The Cambrian Explosion

A sample of the designs that followed Google's first Tensor Processing Unit.

A Comprehensive Deep Dive into High-Speed HBM5 Interconnect: Signal Integrity and Co-Design Challenges

How transmission line effects and power-supply induced jitter make high-speed HBM interconnect scaling one of the most challenging co-design issues in AI racks

Tensordyne's Logarithmic Chip Specs Announced | Emilio Andere posted on the topic | LinkedIn

tensordyne just announced their chip specs. their trick is to turn every multiply into an add using logarithms, a trick from 1962 that everyone tried and gave up on. here's the breakdown: the idea is simple. log(a×b) = log(a) + log(b). store your numbers as logs and every…

PCI Express: Specs, Features, Use Cases and PCIe 7.0

Read this blog to learn what PCI Express is, how PCIe 7.0 improves bandwidth and efficiency, and how features like PAM4, FEC, FLIT mode and AXI support next-generation AI, cloud, HPC and edge systems.

chipify

Note: RF design?

Sandia National Labs SA3000 8085 CPU | The CPU Shack Museum

AI Learns the “Dark Art” of RFIC Design

Freed from intelligibility and aesthetics, AI designs faster

A Deep Dive On China’s “LineShine” All-CPU, Exaflops-Class Supercomputer

It has been nine years since a Chinese HPC supercomputer was at the top of the High Performance Linp ...

A Complete Deep Dive of NVIDIA DWDM Co-Packaged Optics for Scaling beyond 200Gbps

Key physics constraints and architecture challenges for scaling data rates in DWDM - ring modulator physics, clocking, CW-DFB Laser, and package integration

siliconcompiler/lambdapdk: Library of open source PDKs

Library of open source PDKs

NASA Tests Next-gen Radiation-hardened Space Computer Chip - Dataconomy

NASA's High Performance Spaceflight Computing project aims to significantly enhance the computational capabilities of spacecraft, enabling autonomous operations and faster

High-Speed Signal Integrity: Physical Impairments and Equalization Architectures

How signal integrity influences complexity of modern wireline transceiver architecture from first principles

An Overview of AI Accelerators: MAC Operations, DRAM/SRAM, Performance Metrics, and Architecture

Learning from a classic AI accelerator - Eyeriss

A System Architecture Breakdown of a DSP-Based Modern Wireline Transceiver

How high-speed data requirements influence chip architectural complexity

Advanced Packaging: Intel's EMIB vs TSMC's CoWoS

Is Intel's EMIB better than TSMC's CoWoS for AI accelerators? A primer on both, an honest look at the trade-offs, and where it goes from here.

The EDA Primer: From RTL to Silicon

Laying the Groundwork of the Current Chip Design Paradigm

Open Artwork System Interchange Standard

file format used for specification of data structures for photomask production

An Update on the Timing Industry

Q&A with SiTime CEO Rajesh Vashist

RF Engineering is Black Magic

Tribal knowledge of RF design, EV range vs. temperature on the dyno, OpenAI's expanding robotic division, and more.

Disaggregated Inference: How NVIDIA, AWS, and Cerebras Are Rethinking LLM Inference | American Compute

Disaggregated inference started as a software technique for splitting prefill and decode onto separate GPU pools. NVIDIA, Groq, Cerebras, and AWS are now taking it further with chips purpose-built for each phase.

prefill-decode disaggregation

production LLM serving

Memory for AI Accelerators | American Compute

HBM, GDDR, and SRAM compared: how memory hierarchy, bandwidth, and capacity determine AI accelerator performance, cost, and which workloads each chip can serve.

prefill (processing the prompt), which is often compute-bound

decode (token-by-token generation), which is usually memory-bound

Sparse AI Hardware Slashes Energy and Latency

Sparse computing enables leaner, faster AI

Samsung Breaks the 10nm DRAM Barrier With New 4F Cell Structure That Boosts Density By Up to 50%

Samsung has reportedly produced the world's first standalone DRAM module that uses a process tech below 10nm.

Note: The “1x, 1y, 1z, 1a…” naming is just the DRAM industry’s generational shorthand — each step is a shrink within the broad “10nm-class” umbrella, not a distinct architecture change. The progression: |Gen|Approx. node|Era | |---|------------|---------------------------| |1x |~18–19nm |~[2016–2017](tel:2016-2017)| |1y |~17nm |~2018 | |1z |~15–16nm |~[2019–2020](tel:2019-2020)| |1a |~14nm |~2021 | |1b…

How Agentic AI Chip Design Built a Full RISC-V Core

Startup Verkor.io’s agentic AI orchestrated the entire design process from a 219-word prompt

How to Overcome the Advanced Node Physical Verification...

This blog looks at the details of how Synopsys IC Validator can overcome the advanced node physical verification bottleneck.

Panel-Level Packaging's Second Wave Meets Engineering Reality

The cost case is strengthening, but glass, warpage, and bonding yield stand in the way.

Five ai compute architectures every engineer should know cpus gpus tpus npus and lpus compared

Reinventing Embedded Memory: Solving The SRAM Scaling Wall

A new embedded memory architecture with a three-transistor cell.