CXMT's 4F² DDR5 Memory Plan To 'Leapfrog' Samsung & Others By Two Years Is A Paper Tiger, Say Analysts, As Sanctions Push It Into Bitter…

Chinese memory chip manufacturer CXMT's recent claim that it would 'leapfrog' established memory giants Samsung, SK hynix and Micron by two years is nothing but that of a paper tiger, analysts from Rosenblatt believe. CXMT's President, Dr. Cao Kanyu, recently claimed at the…

Note: Standard designs, which are referred to as 6F², have transistors, also referred to as pillars, staggered in an offset grid pattern between the bit and word lines. On the other hand, 4F² optimizes the design by placing the pillars over the interesting bit and word lines to reduce the area of the memory cell. The reason 4F² is able to reduce the area is through vertically stacking the bit line…

Standard designs, which are referred to as 6F², have transistors, also referred to as pillars, staggered in an offset grid pattern between the bit and word lines. On the other hand, 4F² optimizes the design by placing the pillars over the interesting bit and word lines to reduce the area of the…

The reason 4F² is able to reduce the area is through vertically stacking the bit line contacts, capacitors and transistors which are otherwise laid out horizontally in a 6F² cell design.

Intel’s Ex-CEO Pat Gelsinger Says HBM Is A “Hideous Memory,” Replete With Terrible Bit Density, And Thermal And Shoreline Bandwidth Issues…

Intel's ex-CEO cites HBM's terrible bit density, shoreline bandwidth limits, and heat, saying DRAM doesn't like to be hot.

The Tragedy of 3D XPoint (AKA Intel Optane AKA Micron QuantX)

Too early and too late. Can it be resurrected from the dead?

A Stealth Startup Thinks It Just Hacked the Memory Shortage

Kepler Computing claims a new approach to chip design—and a proprietary material—can help end the supply bottlenecks that have sent memory prices surging.

AMD Says A Hybrid-Bonded 3D DRAM Is 17x More Energy Efficient Than An HBM Stack That Relies On Microbumps, But Thermal Hurdles Block…

d-Matrix is tackling the 3D DRAM heat problem by stacking memory beneath the XPU, but atomic-level flatness remains a brutal barrier.

Hot Chips 2026: XCENA and Samsung’s Near-Memory Compute CXL Device

CXL memory expansion, with a side of compute

NVIDIA Unveils NVHBM Memory To Turbocharge AI Chip Speeds By 30%

NVIDIA's NVHBM is a new memory technology that partners can license, offering improved efficiency and performance over standard HBM.

d-Matrix Claims 20x Bandwidth Density Over NVIDIA Rubin In New Chip

The company's ideas aren't novel, but it has solved long-standing challenges with 3D DRAM technology.

d-Matrix’s Raptor 3D DRAM Achieves SRAM-Class Bandwidth at 1/10th the HBM Power by Dropping PHY & Fusing DRAM Beneath the Compute

d-Matrix's Raptor 3D DRAM delivers 100 TB/s bandwidth at 0.37 pJ/bit, offering a high-efficiency alternative to SRAM and HBM for AI workloads

AI Chip Architectures

A look at AI Chip Architectures. NVIDIA, AMD, TPUs, Trainium, Groq, Cerebras.

Hot Chips 2026: Samsung and HBM Base Die Opportunities

Machine learning applications demand ever more memory capacity and bandwidth. Samsung responded by fabricating their HBM base dies on a logic node, which opens up more opportunities

Build Your Own DRAM Supply Model

Wafer starts, die size, yield, HBM mix, node migration impacts, etc. Simple enough to follow, but detailed enough to learn from.

A Deep Dive into SRAM: The Staging Ground of LLM Inference

Fundamentals of SRAM and how SRAM constraints affect array size scaling and LLM inference performance

HBM’s Manufacturing Complexities Mean General-Purpose DRAM Still The Primary Cash Cow For Companies Like Micron; Gross Margins Estimated To…

HBM manufacturing complexities are keeping general-purpose DRAM as Micron’s main cash cow, with DRAM gross margins projected to reach 95% by 2027

Mysterious Case of JetBlue Flight That Went Into Free Fall

Why would a perfectly good plane suddenly go rogue? The answer was disturbing enough to ground 6,000 aircraft.

Demystifying DRAM Read Disturbance: Bridging the Gap Between...

DRAM read disturbance, like RowHammer and RowPress, is a critical robustness issue where accessing DRAM can cause unintended bitflips in other unaccessed DRAM locations. DRAM read disturbance bitflips significantly impact the safe, secure, and reliable operation of DRAM-based…

High Bandwidth Flash: The Full Report

Why HBF for inference decode fits, what it does to the DRAM and NAND markets, a worked cost model, who moves first, and risks

The Memory in Your Thumb Drive Could Fix AI's Big Problem

High Bandwidth Flash offers efficient storage for model weights

CEA-Leti Looks to FeRAM as AI Reshapes Memory Roadmap - EE Times

CEA-Leti’s François Andrieu said it is pushing FeRAM because it could offer a useful combination of density, high endurance, and high speed.

ECC and DDR5

Hamming Codes ECC RAM corrects errors that occur in memory before it gets to the CPU. The most common form of ECC is the Hamming Code [1] which when it has R redundant bits can correct single bit e…

What "Memory Compiler" Actually Means: From Bitcells to GDS Tiling | The Cloudlet

What does a memory compiler actually do? From T-diagrams and 6T bitcells to GDS tiling, LVS, and the symmetry between memory compiler tiling and ML compiler tiling.

Kioxia and Sandisk sample shipping 332-layer 3D NAND

Kioxia and Sandisk haVE started delivering samples of its tenth generation 3D NAND BiCS chips w ...

An Overview of AI Accelerators: MAC Operations, DRAM/SRAM, Performance Metrics, and Architecture

Learning from a classic AI accelerator - Eyeriss

What Is Z-Angle Memory and Why Is Intel Developing It? - HPCwire

Intel announced this week that it’s working with SoftBank subsidiary SAIMEMORY to commercialize Z-Angle Memory (ZAM), an advanced type of DRAM that stacks memory modules vertically. While ZAM chips aren’t expected to become available for at least three years, they could…

NVIDIA cancels Rubin CPX, partners with Groq for LPU | Illia Kasian posted on the topic | LinkedIn

why did NVIDIA cancel the Rubin CPX and replace it with a Groq LPU? LLM inference has two phases. prefill processes the whole prompt at once and is compute-bound. decode generates one token at a time and is memory-bound, reading the full model weights and KV cache for every…

Disaggregated Inference: How NVIDIA, AWS, and Cerebras Are Rethinking LLM Inference | American Compute

Disaggregated inference started as a software technique for splitting prefill and decode onto separate GPU pools. NVIDIA, Groq, Cerebras, and AWS are now taking it further with chips purpose-built for each phase.

prefill-decode disaggregation

production LLM serving

Memory for AI Accelerators | American Compute

HBM, GDDR, and SRAM compared: how memory hierarchy, bandwidth, and capacity determine AI accelerator performance, cost, and which workloads each chip can serve.

prefill (processing the prompt), which is often compute-bound

decode (token-by-token generation), which is usually memory-bound

Samsung Breaks the 10nm DRAM Barrier With New 4F Cell Structure That Boosts Density By Up to 50%

Samsung has reportedly produced the world's first standalone DRAM module that uses a process tech below 10nm.

Note: The “1x, 1y, 1z, 1a…” naming is just the DRAM industry’s generational shorthand — each step is a shrink within the broad “10nm-class” umbrella, not a distinct architecture change. The progression: |Gen|Approx. node|Era | |---|------------|---------------------------| |1x |~18–19nm |~[2016–2017](tel:2016-2017)| |1y |~17nm |~2018 | |1z |~15–16nm |~[2019–2020](tel:2019-2020)| |1a |~14nm |~2021 | |1b…

#semiconductors #dram #memory #ai #artificialintelligence #cloud #cloudcomputing #datacenters #hbm #highbandwidthmemory #automotive #adas…

DRAM Market Shift: From Mobile to Infrastructure (2023–2030) The latest DRAM demand outlook highlights a clear structural transition: memory demand is moving from mobile-driven to infrastructure-driven growth. 1. Infrastructure Becomes Dominant Servers & Workstations grow from…

#ddr4 #lpddr4 #ddr5 #lpddr5x #semiconductors #memoryindustry #supplychain #automotivetech #industrialiot #ai #techstrategy #eol | Nick…

🚨 DDR4 / LPDDR4: The Beginning of the End — or a Strategic Reset? The memory industry is approaching a pivotal inflection point—and the signals are becoming impossible to ignore. Recent developments from Samsung indicate that legacy nodes such as LPDDR4 (and increasingly DDR4)…

Rambus Quietly Builds The Missing Piece Of AI Servers As SOCAMM2 Becomes The Favorite AI Memory Standard

Rambus has announced its LPDDR5X SOCAMM2 memory chipset, a vital component to enable the next-gen compact memory for AI datacenters.

Reinventing Embedded Memory: Solving The SRAM Scaling Wall

A new embedded memory architecture with a three-transistor cell.

A Deep Dive Into Modern Computer Memory: ROM, DRAM, SRAM & Flash

Explore the four key modern memory types: ROM, DRAM, SRAM, and flash, their unique roles, and trade-offs in speed, cost, and storage.

DRAM Chips Perform Functionally-Complete Boolean Operations (ETH Zurich)

A new technical paper titled “Functionally-Complete Boolean Logic in Real DRAM Chips: Experimental Characterization and Analysis” was published by researchers at ETH Zurich. Abstract: “Processing-using-DRAM (PuD) is an emerging paradigm that leverages the analog operational…

How To Stop Row Hammer

What it is, and why this has become such a significant security issue.

Non-binary DDR5 is finally coming to save your wallet • The Register

Need a New Year's resolution? How about stop paying for memory you don't need

The Northwest-AI-Hub which is researching hybrid gain cell memory that combines DRAM's density with

Katherine Bourzac / IEEE Spectrum: The Northwest-AI-Hub, which is researching hybrid gain cell memory that combines DRAM's density with SRAM's speed, gets a $16.3M CHIPS Act grant via the US DOD