Apple's M1 Positioning Mocks the Entire x86 Business Model
Apple is positioning its M1 quite differently from any CPU Intel or AMD has released. The long-term impact on the PC market could be significant.
cpus
Sapphire Rapids CPU Leak: Up to 56 Cores, 64GB of Onboard HBM2
Sapphire Rapids, Intel's next server architecture, looks like a large leap over the just-launched Ice Lake SP.
CPU-based algorithm trains deep neural nets up to 15 times faster than top
Rice University computer scientists have demonstrated artificial intelligence (AI) software that runs on commodity processors and trains deep neural networks 15 times faster than platforms based on graphics ...
The MIPS R4000, part 9: Stupid branch delay slot tricks
Technically legal, but strange.
Deep Dive Into AMD’s “Milan” Epyc 7003 Architecture
The “Milan” Epyc 7003 processors, the third generation of AMD’s revitalized server CPUs, is now in the field, and we await the entry of the “Ice Lake”
The Rise, Fall and Revival of AMD (2020)
AMD is one of the oldest designers of large scale microprocessors and has been the subject of polarizing debate among technology enthusiasts for nearly 50 years. Its...
The Third Time Charm Of AMD’s Milan Epyc Processors
With every passing year, as AMD first talked about its plans to re-enter the server processor arena and give Intel some real, much needed, and very direct
AMD's Reliance on TSMC Isn't Harming the Company's Growth Prospects - Extre
Intel Processor Names, Numbers and Generation List
Understanding Intel® processor names and numbers helps identify the best laptop, desktop, or mobile device CPU for your computing needs.
Threadripper 3990X: The Quest To Compile 1 BILLION Lines Of C++ On 64 Cores
Intel Core i9-10850K Review: The Real Intel Flagship
Use `nproc` and not grep /proc/cpuinfo
There’s something really quite subtle about how the nproc utility from GNU coreutils works. If you look at the man page, it’s even the very first sentence: Print the number of processin…
How Debuggers Work: Getting and Setting x86 Registers
In this article, I would like to shortly describe the methods used to dump and restore the different kinds of registers on 32-bit and 64-bit x86 CPUs. The first part will focus on General Purpose Registers, Debug Registers and Floating-Point Registers up to the XMM registers…
TamaGo - bare metal Go for ARM SoCs
TamaGo - ARM/RISC-V bare metal Go.
Performance analysis & tuning on modern CPU - DEV Community ????
They say "performance is king'... It was true a decade ago and it certainly is now. With more and mor...
An ex-ARM engineer critiques RISC-V
RISC-V.md · GitHub
Optimizing 128-bit Division
When it comes to hashing, sometimes 64 bit is not enough, for example, because of birthday paradox — the hacker can iterate through random $latex 2^{32}$ entities and it can be proven that wi…
x86 instruction listings
The x86 instruction set refers to the set of instructions that x86-compatible microprocessors support. The instructions are usually part of an executable program, often stored as a computer file and executed on the processor.
Fujitsu Begins Shipping Supercomputer Fugaku - Fujitsu Global
Fujitsu Limited today announced that it began shipping the supercomputer Fugaku, which is jointly developed with RIKEN and promoted by the Ministry of Education, Culture, Sports, Science and Technology with the aim of starting general operation between 2021 and 2022. The first…
Let’s Build a Simple Interpreter. Part 18: Executing Procedure Calls
Do the best you can until you know better. Then when you know better, do better. ― Maya Angelou
96-Core Processor Made of Chiplets
64 Core Threadripper 3990X CPU Review
bhive/README.md at master · ithemal/bhive
It’s a Cascade of 14nm CPUs: AnandTech’s Intel Core i9-10980XE Review
Counting FLOPS and other CPU counters in Python
On the Linux command line it is fairly easy to use the perf command to measure number of floating point operations (or other performance metrics). (See for example this old blog post ) with this approach it is not easy to get a fine grained view of how different stages of…
Intel 10th Gen Comet Lake CPU Family Leaks With 10-Core, 20-Thread LGA-1200
Recent leaks may shed some light on Intel's upcoming mainstream desktop Comet Lake-S CPUs.
Intel Tremont CPU Microarchitecture: Power Efficient, High-Performance x86
Intel's Tremont CPU microarchitecture will be the foundation of a next-generation, low-power processors that target a wide variety of products across
Intel's new Atom Microarchitecture: The Tremont Core in Lakefield
RISC-V from scratch 2: Hardware layouts, linker scripts, and C runtimes
A post describing how C programs get to the main function. Devicetree layouts, linker scripts, minimal C runtimes, GDB and QEMU, basic RISC-V assembly, and other topics are reviewed along the way.
“Essentials of Garbage Collectors” full course is now available
Course overview Memory leaks and dangling pointers are the main issues of the manual memory management. You delete a parent node in a linked list, forgetting to delete all its children first -- and your
Avoiding Instruction Cache Misses
Excessive instruction cache misses are the kind of a performance problem that's going to appear only in larger codebases. In this article, I'm describing some ideas on how to deal with this issue.
Amp
PrincetonUniversity/accelerator-wall: Repository for the tools and non-comm
Repository for the tools and non-commercial data used for the "Accelerator wall" paper. - PrincetonUniversity/accelerator-wall
Benchmarking Amazon's ARM Graviton CPU With EC2's A1 Instances
Monday night Amazon announced the new 'A1' instance type for the Elastic Compute Cloud (EC2) that is powered by their own 'Graviton' ARMv8 processors.
ARM is the NNSA’s New Secret Weapon
It might have been difficult to see this happening a mere few years ago, but the National Nuclear Security Administration and one of its key
Google’s new Bristlecone processor brings it one step closer to quantum sup
Every major tech company is looking at quantum computers as the next big breakthrough in computing. Teams at Google, Microsoft, Intel, IBM and various