Memory Allocation
A visual introduction to memory allocation.
cpus
ARM’s Cortex A53: Tiny But Important
Tech enthusiasts probably know ARM as a company that develops reasonably performant CPU architectures with a focus on power efficiency.
Intel CPU Die Topology - by Jason Rahman - Delayed Branch
Over the past 10-15 years, per-core throughput increases have slowed, and in response CPU designers have scaled up core counts and socket counts to continue increasing performance across generations of new CPU models.
Reverse-engineering the division microcode in the Intel 8086 processor
While programmers today take division for granted, most microprocessors in the 1970s could only add and subtract — division required a sl...
Hacker News
While microprocessors are used in various applications, they are precluded from the use in high-energy physics applications due to the harsh radiation present. To overcome this limitation a...
Interconnect Under the Spotlight as Core Counts Accelerate - SemiWiki
In the march to more capable, faster, smaller, and lower…
Why AI Inference Will Remain Largely On The CPU
Sponsored Feature: Training an AI model takes an enormous amount of compute capacity coupled with high bandwidth memory. Because the model training can be
RISC-V In The Datacenter Is No Risky Proposition
It was only a matter of time, perhaps, but the skyrocketing costs of designing chips is colliding with the ever-increasing need for performance,
China’s flagship CPU designer puts on a brave face amid US sanctions
Chinese chip designer Loongson, which has tried to reduce the country’s reliance on Intel and AMD, is developing its own general-purpose GPU despite being added to a US trade blacklist.
Make your sklearn models up to 100 times faster
How to considerable reduce training time changing only 1 line of code
The basics of Arm64 Assembly - by Diego Crespo
Just one instruction at a time!
Google increases server life to six years, will save billions of dollars
While Meta ups to five years
More CPU Cores Isn’t Always Better, Especially In HPC
If a few cores are good, then a lot of cores ought to be better. But when it comes to HPC this isn’t always the case, despite what the Top500 ranking –
Inside the 8086 processor's instruction prefetch circuitry
The groundbreaking 8086 microprocessor was introduced by Intel in 1978 and led to the x86 architecture that still dominates desktop and se...
https://squeaky.ai/blog/development/how-switching-to-aws-graviton-slashed-our-infrastructure-bill-by-35-percent
Four Cornerstones of CPU Performance.
Monolithic Sapphire Rapids
Absolute Reticle Limit
Intel’s Redwood Cove: Baby Steps are Still Steps
Intel’s Meteor Lake chip signaled a change in Intel’s mobile strategy, moving away from the monolithic designs that had characterized Intel’s client designs for more than a decade.
Performance Benefits of Using Huge Pages for Code. | Easyperf
Use One Big Server - Speculative Branches
New working speculative execution attack sends Intel and AMD scrambling
Both companies are rolling out mitigations, but they add overhead of 12 to 28 percent.
A new vulnerability in Intel and AMD CPUs lets hackers steal encryption keys
Hertzbleed attack targets power-conservation feature found on virtually all modern CPUs.
HPC-oriented Latency Numbers Every Programmer Should Know
HPC-oriented Latency Numbers Every Programmer Should Know · GitHub
5.5 mm in 1.25 nanoseconds | Random ASCII – tech blog of Bruce Dawson
In 2004 I was working for Microsoft in the Xbox group, and a new console was being created. I got a copy of the detailed descriptions of the Xbox 360 CPU and I read it through multiple times and su…
Top-Down performance analysis methodology. | Easyperf
You Won’t Believe This One Weird CPU Instruction! - Vaibhav Sagar
larsbrinkhoff/awesome-cpus: All CPU and MCU documentation in one place
All CPU and MCU documentation in one place.
How FPGAs Can Take On GPUs And Knights Landing
Nallatech doesn't make FPGAs, but it does have several decades of experience turning FPGAs into devices and systems that companies can deploy to solve
Analysis and Comparison of Performance and Power Consumption of Neural Netw
In this work, we analyze the performance of neural networks on a variety of heterogenous platforms. We strive to find the best platform in terms of raw benchmark performance, performance per watt a…
The Story of the IBM Pentium 4 64-bit CPU | The CPU Shack Museum
Intel Processor Trace Part4. Better profiling experience. | Easyperf
Intel Processor Trace Part3. Analyzing performance glitches. | Easyperf
Domain-Specific Hardware Accelerators – Communications of the ACM
Sushi Roll: A CPU research kernel with minimal noise for cycle-by-cycle micro-architectural introspection
Precise timing of machine code with Linux perf. | Easyperf
Getting started with bare-metal assembly
For Better Computing, Liberate CPUs From Garbage Collection
An accelerator unit improves both the performance and efficiency of a system by taking over one simple task
openhwgroup/cva6: The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux - openhwgroup/cva6
cirosantilli/x86-bare-metal-examples: Dozens of minimal operating systems to learn x86 system programming. Tested on Ubuntu 17.10 host in…
Dozens of minimal operating systems to learn x86 system programming. Tested on Ubuntu 17.10 host in QEMU 2.10 and real hardware. Userland cheat at: https://github.com/cirosantilli/linux-kernel-modu...
To reinvent the processor
A detailed, critical, technical essay on upcoming CPU architectures.
1804
Software optimization resources. C++ and assembly. Windows, Linux, BSD, Mac OS X
Software optimization manuals for C++ and assembly code. Intel and AMD x86 microprocessors. Windows, Linux, BSD, Mac OS X. 16, 32 and 64 bit systems. Detailed descriptions of microarchitectures.
Estimating branch probability using Intel LBR feature. | Easyperf
How does tomasulos algorithm work
Does an AMD Chiplet Have a Core Count Limit?
Did IBM Just Preview The Future of Caches?
Gutting Decades Of Architecture To Build A New Kind Of Processor
There are some features in any architecture that are essential, foundational, and non-negotiable. Right up to the moment that some clever architect shows
AMD 3D Stacks SRAM Bumplessly
AMD recently unveiled 3D V-Cache, their first 3D-stacked technology-based product. Leapfrogging contemporary 3D bonding technologies, AMD jumped directly into advanced packaging with direct bonding and an order of magnitude higher wire density.
Intel: AMD Threat Is Finished (NASDAQ:INTC)
Although competition from Arm is increasing, AMD remains Intel’s biggest competitor, as concerns of losing market share weigh on Intel’s valuation.
New 'Morpheus' CPU Design Defeats Hundreds of Hackers in DARPA Tests - Extr
A new CPU design has won accolades for defeating the hacking efforts of nearly 600 experts during a DARPA challenge. Its approach could help us close side-channel vulnerabilities in the future.