Intel 10th Gen Comet Lake CPU Family Leaks With 10-Core, 20-Thread LGA-1200
Recent leaks may shed some light on Intel's upcoming mainstream desktop Comet Lake-S CPUs.
semiconductors
What’s The Best Advanced Packaging Option?
A dizzying array of choices and options pave the way for the next phase of scaling.
Intel Tremont CPU Microarchitecture: Power Efficient, High-Performance x86
Intel's Tremont CPU microarchitecture will be the foundation of a next-generation, low-power processors that target a wide variety of products across
Intel's new Atom Microarchitecture: The Tremont Core in Lakefield
Building An MRAM Array
Why MRAM is so attractive.
New chips for machine intelligence
CMOS Circuit Design, Layout, and Simulation
AI Inference Memory System Tradeoffs
TOPS isn't all you need to know about an inference chip.
RISC-V from scratch 2: Hardware layouts, linker scripts, and C runtimes
A post describing how C programs get to the main function. Devicetree layouts, linker scripts, minimal C runtimes, GDB and QEMU, basic RISC-V assembly, and other topics are reviewed along the way.
Manufacturing memory means scribing silicon in a sea of sensors | Ars Techn
“Industry 4.0” is already here for some companies—especially silicon foundries.
TSMC Talks 7nm, 5nm, Yield, And Next-Gen 5G And HPC Packaging
An update on TSMC current and forthcoming logic process nodes as well as their next-generation advanced packaging technologies.
First Programmable Memristor Computer
Michigan team builds memristors atop standard CMOS logic to demo a system that can do a variety of edge computing AI tasks
In Memory And Near-Memory Compute
How much power is spent storing and moving data.
Startup Runs AI in Novel SRAM
Areanna claims that a custom SRAM delivers 100 TOPS/W on deep learning, but it’s early days for the startup.
About Us - AnySilicon
“The Google of the Semiconductor Industry” Founded in 2011, AnySilicon is the best way to explore, find and contact semiconductor service providers and IP vendors online. Our vision is to be the first place ASIC engineers and decision makers go to search for semiconductor…
Avoiding Instruction Cache Misses
Excessive instruction cache misses are the kind of a performance problem that's going to appear only in larger codebases. In this article, I'm describing some ideas on how to deal with this issue.
RAMBleed
Lightelligence releases prototype of its optical AI accelerator chip
Boston-based startup Lightelligence's optical machine learning accelerator has entered prototyping stage, the startup announced.
Memory Architectures In AI: One Size Doesn't Fit All
Comparing different machine learning use-cases and the architectures being used to address them.
Startup Sheds Some Light On Optical Processing
Optalysys, a startup based in the United Kingdom, has introduced an entry-level optical coprocessor, the first such system of its kind on the market. The
Arrow Electronics API | ProgrammableWeb
http://developers.arrow.com/api/
API Solutions | DigiKey
DigiKey offers a complete set of APIs to share information and automate the ordering process.
PrincetonUniversity/accelerator-wall: Repository for the tools and non-comm
Repository for the tools and non-commercial data used for the "Accelerator wall" paper. - PrincetonUniversity/accelerator-wall
A MEMS Device Harvests Vibrations to Power the IoT
Scientists in Japan have developed a MEMS energy harvester charged by an off-chip electret
Use Inference Benchmarks Similar To Your Application
How the wrong benchmark can lead to incorrect conclusions.
Introduction to Supercapacitors
Get a primer on the basics of supercapacitors, their functionality, and which applications they're best for.
Benchmarking Amazon's ARM Graviton CPU With EC2's A1 Instances
Monday night Amazon announced the new 'A1' instance type for the Elastic Compute Cloud (EC2) that is powered by their own 'Graviton' ARMv8 processors.
ARM is the NNSA’s New Secret Weapon
It might have been difficult to see this happening a mere few years ago, but the National Nuclear Security Administration and one of its key
Five Rules For Correlating Rule-based And Field Solver Parasitic Extraction
Accurately determine parasitic effects with the proper set up of two different methods.
Right product, right time, right location: Quantifying the semiconductor su
A new metric can help companies pinpoint performance issues on the semiconductor supply chain.
Emerging Memories Today: Understanding Bit Selectors - The Memory Guy Blog
The previous post in this series (excerpted from the Objective Analysis and Coughlin Associates Emerging Memory report) explained why emerging memories are necessary. Oddly enough, this series will explain bit selectors before defining all of the emerging memory technologies…
Why Chips Die
Why Chips Die Semiconductor devices face many hazards before and after manufacturing that can cause them to fail prematurely.
Major Pure-Play Foundries Revenue Per Wafer 2017-2018
The average revenue generated from processed wafers among the four biggest pure-play foundries (TSMC, GlobalFoundries, UMC, and SMIC) is expected to be $1,138 in 2018, when expressed in 200mm-equivalent wafers, which is essentially flat from $1,136 in 2017, according to a new…
Process Corner Explosion
Process Corner Explosion, At 7nm and below, modeling what will actually show up in silicon is a lot more complicated.
Minimizing Chip Aging Effects
Understanding aging factors within a design can help reduce the likelihood of product failures.
Processing In Memory
Processing In Memory Growing volume of data and limited improvements in performance create new opportunities for approaches that never got off the ground.
Worldwide Location of Wafer Fabs – Interactive Map
Wafer fabs are the backbone of every electronic product. Every chip consists of a piece of silicon that is produced in a wafer fab. Wafer fabs play a key role in the customer, medical and automotive markets because the are they enabler of innovative technologies. There are many…
An Intro to Integer Programming for Engineers: Simplified Bus Scheduling
Explore what’s new, what’s next, and what should be on your radar in the world of transportation. Our insights are supported by real-world data from our partners across the globe.
Electronic Parts by Category - Octopart
Overclocked Micron GDDR6 Memory Can Hit 20Gbps Speeds For Next Gen GPUs
Micron notes that GDDR6 has silicon changes, channel enhancements, and talks a bit about performance measurements of the new memory.
Cambricon, Makers of Huawei's Kirin NPU IP, Build A Big AI Chip and PCIe Ca
Alchip Minimizes Dynamic Power For High-Performance Computing ASICs
Alchip Minimizes Dynamic Power for High-Performance Computing ASICs How a fabless chipmaker successfully reduced power consumption within its fishbone clock tree methodology.
Tearing Apart Google’s TPU 3.0 AI Coprocessor
Google did its best to impress this week at its annual IO conference. While Google rolled out a bunch of benchmarks that were run on its current Cloud TPU
Google Announces 8x Faster TPU 3.0 For AI, Machine Learning - ExtremeTech
Google's new TPUs are here -- and they're quite a bit faster than last year's model.
gplEDA Homepage
How Does Xilinx Use Its Logic Fabric to Implement Efficient Multipliers?
This article will review the structure of the binary multipliers that use the look-up tables (LUTs) in the Xilinx logic fabric.
Comparing Low Power Wireless Technologies (Part 3) | DigiKey
Low power wireless technologies are adapting to the Internet of Things by including IP connectivity and mesh networking.
Comparing Low-Power Wireless Technologies (Part 1) | DigiKey
The multitude of short-range wireless technologies provides engineers with optimized solutions for their applications, but makes careful selection paramount.
To Speed Up AI, Mix Memory and Processing
New computing architectures aim to extend artificial intelligence from the cloud to smartphones