aolofsson/awesome-opensource-hardware: List of awesome open source hardware tools, generators, and reusable designs
List of awesome open source hardware tools, generators, and reusable designs - aolofsson/awesome-opensource-hardware
sram
Safeguarding SRAMs From IP Theft (Best Paper Award)
A technical paper titled “Beware of Discarding Used SRAMs: Information is Stored Permanently” was published by researchers at Auburn University. The paper won “Best Paper Award” at the IEEE International Conference on Physical Assurance and Inspection of Electronics (PAINE) Oct…
Cerebras Reveals Andromeda, a 13.5 Million Core AI Supercomputer
The world's largest chip scales to new heights.
How Memory Design Optimizes System Performance
Changes are steady in the memory hierarchy, but how and where that memory is accessed is having a big impact.
Ultimate Guide: Clock Tree Synthesis
A vast majority of modern digital integrated circuits are synchronous designs. They rely on storage elements called registers or flip-flops, all of which change their stored data in a lockstep manner with respect to a control signal called the clock. In many ways, the clock…
DRAM Thermal Issues Reach Crisis Point
Increased transistor density and utilization are creating memory performance issues.
CXL: Protocol for Heterogenous Datacenters
Let's learn more about the world's most important manufactured product. Meaningful insight, timely analysis, and an occasional investment idea.
Nvidia Research Plots A Course To Multiple Multichip GPU Engines
There are two types of packaging that represent the future of computing, and both will have validity in certain domains: Wafer scale integration and
Ten Lessons From Three Generations Shaped Google’s TPUv4i - 2021-jouppi.pdf
SRAM vs. DRAM: The Future of Memory - EE Times
EE Times Compares SRAM vs. DRAM, Common Issues With Each Type Of Memory, And Takes A Look At The Future For Computer Memory.
SweRV - An Annotated Deep Dive
An Introduction to Semiconductor Economics
This blog post is in response to a recent topic on the Parallella forum regarding Adapteva’s chip cost efficiency (GFLOPS/$): [forum discussion thread]. I had to be a little vague on some poi…
Synopsys Blog | Latest Insights on EDA, IP & Systems Design
Explore Synopsys Blog for the latest insights and trends in EDA, IP, and Systems Design. Stay updated with expert articles and industry news.
Domain-Specific Hardware Accelerators – Communications of the ACM
Effect of Design on Transistor Density - Semiwiki
I have written a lot of articles looking at leading…
How to make your own deep learning accelerator chip!
Currently there are more than 100 companies all over the world building ASIC’s (Application specific integrated circuit) or SOC’s (System…
Using Memory Differently To Boost Speed
Getting data in and out of memory faster is adding some unexpected challenges.
DRAM Tradeoffs: Speed Vs. Energy
Experts at the Table: Which type of DRAM is best for different applications, and why performance and power can vary so much.
TOPS, Memory, Throughput And Inference Efficiency
Evaluate inference accelerators to find the best throughput for the money.
Next-Gen Chips Will Be Powered From Below
Buried interconnects will help save Moore's Law
Impact Of GAA Transistors At 3/2nm
Some things will get better from a design perspective, while others will be worse.
Bumps Vs. Hybrid Bonding For Advanced Packaging
New interconnects offer speed improvements, but tradeoffs include higher cost, complexity, and new manufacturing challenges.
AMD 3D Stacks SRAM Bumplessly
AMD recently unveiled 3D V-Cache, their first 3D-stacked technology-based product. Leapfrogging contemporary 3D bonding technologies, AMD jumped directly into advanced packaging with direct bonding and an order of magnitude higher wire density.
11 Ways To Reduce AI Energy Consumption
Pushing AI to the edge requires new architectures, tools, and approaches.
Overcoming Challenges In Next-Generation SRAM Cell Architectures
SVT: Six Stacked Vertical Transistors
SRAM cell architecture introduction: design and process challenges assessment.
List of semiconductor fabrication plants - Wikipedia
This is a list of semiconductor fabrication plants. A semiconductor fabrication plant is where integrated circuits (ICs), also known as microchips, are manufactured. They are either operated by Integrated Device Manufacturers (IDMs) that design and manufacture ICs in-house and…
New And Innovative Supply Chain Threats Emerging
But so are better approaches to deal with thorny counterfeiting issues.
Making Full Memory IP Robust During Design - Semiwiki
Looking at a typical SoC design today it's likely to…
Intel Networking: Not Just A Bag Of Parts
What is the hardest job at Intel, excepting whoever is in charge of the development of chip etching processes and the foundries that implement it? We
Domain-Specific Hardware Accelerators | July 2020 | Communications of the A
TSMC Details 5 nm
TSMC details its 5-nanometer node for mobile and HPC applications. The process features the industry's highest density transistors with a high-mobility channel and highest-density SRAM cells.
96-Core Processor Made of Chiplets
Brian Piercy on LinkedIn: The Surprising Value of Obvious Insights
"...Google's people analytics experts had been studying how to onboard new hires effectively. They came back with a list of tips. Here’s the one that jumped…
A Look at Cerebras Wafer-Scale Engine: Half Square Foot Silicon Chip
A look at Cerebras Wafer-Scale Engine (WSE), a chip the size of a wafer, packing over 400K tiny AI cores using 1.2 trillion transistors on a half square foot of silicon.
Building An MRAM Array
Why MRAM is so attractive.
New chips for machine intelligence
AI Inference Memory System Tradeoffs
TOPS isn't all you need to know about an inference chip.
Buried Power Lines Make Memory Faster - IEEE Spectrum
Researchers at imec explore strategy that could make memory more efficient and pack in more transistors
Startup Runs AI in Novel SRAM
Areanna claims that a custom SRAM delivers 100 TOPS/W on deep learning, but it’s early days for the startup.
Use Inference Benchmarks Similar To Your Application
How the wrong benchmark can lead to incorrect conclusions.
Emerging Memories Today: Understanding Bit Selectors - The Memory Guy Blog
The previous post in this series (excerpted from the Objective Analysis and Coughlin Associates Emerging Memory report) explained why emerging memories are necessary. Oddly enough, this series will explain bit selectors before defining all of the emerging memory technologies…
Processing In Memory
Processing In Memory Growing volume of data and limited improvements in performance create new opportunities for approaches that never got off the ground.
Imperfect Silicon, Near-Perfect Security
Imperfect Silicon, Near-Perfect Security Physically unclonable functions (PUF) seem tailor-made for IoT security.
The Northwest-AI-Hub which is researching hybrid gain cell memory that combines DRAM's density with
Katherine Bourzac / IEEE Spectrum: The Northwest-AI-Hub, which is researching hybrid gain cell memory that combines DRAM's density with SRAM's speed, gets a $16.3M CHIPS Act grant via the US DOD
Hybrid Memory Designed to Cut AI Energy Use
Researchers developing dense, speedy hybrid gain cell memory recently got a boost from CHIPS Act funding
Clash of the Foundries: Gate All Around + Backside Power at 2nm
Fab Cost, WFE Implications, Backside Power Details