On-Chip Power Distribution Modeling Becomes Essential Below 7nm
Why and when it's needed, and what tools and technologies are required.
semiconductors
Cerebras Reveals Andromeda, a 13.5 Million Core AI Supercomputer
The world's largest chip scales to new heights.
Startup Knocks Down Chiplet Hurdles with High-performance Link
Eliyan is emerging from stealth mode, unveiling the successful tapeout of its high-performance UCIe-compliant die-to-die interconnect technology in 5 nm process.
TSMC Grants a Sweep of EDA Certifications for New Process Nodes
To ensure that designers have the right tools for the job, TSMC announced a slew of EDA tool certifications for its most advanced processes—ranging from 3 nm nodes to 3D semiconductor integration.
Introduction to Extrinsic Semiconductors
Extrinsic semiconductors have been doped with specific chemicals. This process helps to modify the electrical properties of a relatively pure semiconductor crystal.
What's different about next-gen transistors | Hacker News
What's Different About Next-Gen Transistors
Advanced etch holds key to nanosheet FETs; evolutionary path for future nodes.
Biden Just Clobbered China’s Chip Industry
The latest American trade restrictions could significantly set back China’s semiconductor ambitions.
Four Cornerstones of CPU Performance.
Researchers Develop Transistor-free Compute-in-Memory Architecture
Using new materials, UPenn researchers recently demonstrated how analog compute-in-memory circuits can provide a programmable solution for AI computing.
What Time is It? A Timing Market Primer and Overview
How do we keep track of time? A deeper look into Quartz timers and the emerging field of MEMS
Decreasing Refresh Latency of Off-the-Shelf DRAM Chips
A new technical paper titled “HiRA: Hidden Row Activation for Reducing Refresh Latency of Off-the-Shelf DRAM Chips” was published by researchers at ETH Zürich, TOBB University of Economics and Technology and Galicia Supercomputing Center (CESGA). Abstract “DRAM is the building…
Monolithic Sapphire Rapids
Absolute Reticle Limit
How Memory Design Optimizes System Performance
Changes are steady in the memory hierarchy, but how and where that memory is accessed is having a big impact.
Ultimate Guide: Clock Tree Synthesis
A vast majority of modern digital integrated circuits are synchronous designs. They rely on storage elements called registers or flip-flops, all of which change their stored data in a lockstep manner with respect to a control signal called the clock. In many ways, the clock…
Performance Benefits of Using Huge Pages for Code. | Easyperf
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Industry Structure: Fabs are in Favor - LTAs are the Tell
Long Term agreements, particularly the NCNR order is a relative newcomer this cycle. Let's see how they are holding up. The Industry Structure is showing that Fabs are in charge.
Perspective | Electronics are built with death dates. Let’s not keep them a secret.
Our analysis of 14 popular consumer devices found most could stop working in 3 to 4 years because of irreplaceable batteries. Here’s how we get the tech industry to design products that last longer — and do less damage to the environment.
GlobalFoundries joins Google's open-source silicon initiative
Google announced in a blog on August 3 that GlobalFoundries (GF) is participating in its open-source silicon initiative as a new partner, calling the new partnership a milestone in the foundry ecosystem market.
Semis for Everyone?
Google is promoting the growth of open source tools for designing semis. The science fiction version of this story leads to everyone designing chips, the reality is going to be much narrower, but s…
SkyWater and Google expand open source program to new 90nm technology | Goo
Over the last two years, Google and SkyWater Technology have partnered to make building open silicon accessible to all developers
Moneyball for engineers: What the semiconductor industry can learn from sports
R&D leaders can boost productivity by using advanced analytics to create stronger, faster engineering teams.
New working speculative execution attack sends Intel and AMD scrambling
Both companies are rolling out mitigations, but they add overhead of 12 to 28 percent.
Memristive, Spintronic, and 2D‐Materials‐Based Devices to Improve and Compl
Moore's law has slowed down and, with the rise of data-intensive applications, like machine learning, new approaches to computing hardware are needed. The perspective explores the role of memristive,...
CXL: Protocol for Heterogenous Datacenters
Let's learn more about the world's most important manufactured product. Meaningful insight, timely analysis, and an occasional investment idea.
Ayar Labs: Solving Bandwidth and Power Bottlenecks with Optical I/O
Ayar Labs solves bandwidth and power bottlenecks by moving data using light. We built the world's first optical I/O chiplets.
Intel® Silicon Photonics
Intel® Silicon Photonics combines the manufacturing scale and capability of silicon with the power of light onto a single chip.
Intel Showcases a Photonics “First” — an Eight-wavelength Laser Array - News
Intel Lab researchers push photonics one step further by demonstrating a tightly controlled, highly integrated eight-wavelength laser.
CXL Enables Microsoft Azure To Cut Server Capital Expenditures By Hundreds
Intel announces silicon photonics advancement towards optical I/O
Intel has demonstrated an eight-wavelength laser array on a silicon wafer paving the way for the next generation of integrated silicon photonics products.
An Introduction to MEMS Vibratory Gyroscopes
Microelectromechanical systems (MEMS) vibratory gyroscopes can be a bit mysterious and math-intensive. Let's break the math down, and go over gyroscope basics and structures.
Can You Trust Semiconductor Capital Equipment Firms? Supply Chain Or Techno
The Basics of Electrical Engineering Standards
Get a high-level introduction to how standards play into the EE world.
A new vulnerability in Intel and AMD CPUs lets hackers steal encryption keys
Hertzbleed attack targets power-conservation feature found on virtually all modern CPUs.
PCI Express 7.0 standard provides eight times the bandwidth of today’s conn
PCI-SIG has drafted the PCIe 7.0 spec and aims to finalize it in 2025.
High-Performance 5G IC Designs Need High-Performance Parasitic Extraction
The high frequencies and data rates involved in 5G designs makes layout verification all the more important.
Die Size And Reticle Conundrum – Smaller Isn’t Always Better – Cost Model W
GaN Systems Cup 2022 design competition underway
Challenge to create GaN-based 400V photovoltaic power supply
Designing and Simulating Low-Voltage CMOS Circuits Using Four-Parameter Mod
New technical paper titled “Bridging the Gap between Design and Simulation of Low-Voltage CMOS Circuits” from researchers at Federal University of Santa Catarina, Brazil. Abstract “This work proposes a truly compact MOSFET model that contains only four parameters to assist an…
Thermal Management Challenges and Requirements of 3 types of Microelectroni
New technical paper titled “A Review on Transient Thermal Management of Electronic Devices” from researchers at Indian Institute of Technology Bombay. Abstract “Much effort in the area of electronics thermal management has focused on developing cooling solutions that cater to…
Will optics replace copper interconnects? We asked Ayar Labs
Star Trek's glowing circuit boards may not be so crazy
Practical Power Beaming Gets Real
A century later, Nikola Tesla’s dream comes true
Another Firing Among Google’s A.I. Brain Trust, and More Discord (Published 2022)
The researchers are considered a key to the company’s future. But they have had a hard time shaking infighting and controversy over a variety of issues.
The X-Ray Tech That Reveals Chip Designs
When you’re baking a cake, it’s hard to know when the inside is in the state you want it to be. The same is true—with much higher stakes—for microelectronic chips: How can engineers confirm that what’s inside has truly met the intent of the designers? How can a semiconductor…
Sandia reports GaN diode with record 6.4kV breakdown ultrafast devices step
Target is 20kV, to protect electric grid from electromagnetic pulse
Designing a 2048-Chiplet, 14336-Core Waferscale Processor
Challenges and troubleshooting employed to design a 2048-chiplet, 14,336-core waferscale processor system.
Semiconductor Engineering - Technical
Semiconductor Engineering's collection of technical papers for the chip industry.
5.5 mm in 1.25 nanoseconds | Random ASCII – tech blog of Bruce Dawson
In 2004 I was working for Microsoft in the Xbox group, and a new console was being created. I got a copy of the detailed descriptions of the Xbox 360 CPU and I read it through multiple times and su…
Nvidia Research Plots A Course To Multiple Multichip GPU Engines
There are two types of packaging that represent the future of computing, and both will have validity in certain domains: Wafer scale integration and