From idea to chip design in minutes! TT09 Closes in TT09 Closes in 44 DAYS 44 HOURS 44 MINS 44 SECS Tiles PCBs Tiny Tapeout is an educational project that makes it easier and cheaper than ever to get your designs manufactured on a real chip! Read the paper here. See what other…
Mike Wheatley / SiliconANGLE: Cerebras open sources seven GPT-based LLMs, ranging from 111M to 13B parameters and trained using its Andromeda supercomputer for AI, on GitHub and Hugging Face
Regardless of which one wins, they will cut greenhouse gases by billions of tonnes
As the US boosts production of silicon chips, an American journalist goes inside TSMC, the mysterious Taiwanese company at the center of the global industry.
A new way of making wafer-scale electronics out of atomically thin sheets.
Faster masks, less power.
Comprehensive up-to-date news coverage, aggregated from sources all over the world by Google News.
Chinese chip designer Loongson, which has tried to reduce the country’s reliance on Intel and AMD, is developing its own general-purpose GPU despite being added to a US trade blacklist.
ReRAM startup Intrinsic Semiconductor Technologies has raised $9.73 million to expand its engineering team and bring its product to market.
Lead SiC test & burn-in customer boosting production of power devices for EVs
A list of artificial intelligence used in semiconductor manufacturing tools from February 2023.
Introduction
China-based semiconductor manufacturers, in the wake of geopolitical risks, are expected to keep up with their capacity expansion strategies going into 2023 with a good number of projects already in construction, according to DIGITIMES Research's latest report covering the…
Mar. 13, 2023 —- According to TrendForce’s latest survey of the global foundry market, electronics brands began adjusting their inventories in 2Q22, but foundries were unable to rapidly adapt to this development because they reside in the more upper portion of the supply chain…
Kuo-Hua Chou, special to DIGITIMES Asia
Just one instruction at a time!
Marvell has had a large and profitable I/O and networking silicon business for a long time, but with the acquisitions of Inphi in October 2020 and of
A new technical paper titled “APOSTLE: Asynchronously Parallel Optimization for Sizing Analog Transistors Using DNN Learning” was published by researchers at UT Austin and Analog Devices. Abstract “Analog circuit sizing is a high-cost process in terms of the manual effort…
It may be the only way to keep up with environmental power regulations
The $10,000 Nvidia A100has become one of the most critical tools in the artificial intelligence industry,
AI firm Synopsys has announced that its DSO.ai tool has successfully aided in the design of 100 chips, and it expects that upward trend to continue.
We have been very public about how reliable Samsung SSDs have been in the past, so we wanted to explain why we are now moving part of our line to Sabrent.
New applications require a deep understanding of the tradeoffs for different types of DRAM.
Security IP cores are blocks that provide security features for integrated circuits (ICs) and systems-on-chips (SoCs). It includes encryption, decryption, authentication, and key management functions that protect against unauthorized access or hacking. The IP core can be…
Here, I provide an in-depth analysis of GPUs for deep learning/machine learning and explain what is the best GPU for your use-case and budget.
If a few cores are good, then a lot of cores ought to be better. But when it comes to HPC this isn’t always the case, despite what the Top500 ranking –
Covering EUV Lithography, ASML, and everything in between from how it all works to their impact on the world and what it all means.
Book repository "Analysis and Design of Elementary MOS Amplifier Stages" - bmurmann/Book-on-MOS-stages
— RetiredEngineer® (@chiakokhua)
The following is a list of my articles on various topics. Besides technical articles, news pieces that might have useful technical information are also included. You can find my articles on FPGA...
Learn about voltage waves and how they relate to an important basic concept of radio frequency (RF) circuit design: transmission lines.
Industry sources say TSMC is considering lowering 3nm prices to stimulate interest from chip designers
High performance and high transistor density come at a cost
Need a New Year's resolution? How about stop paying for memory you don't need
Interconnects—those sometimes nanometers-wide metal wires that link transistors into circuits on an IC—are in need of a major overhaul. And as chip fabs march toward the outer reaches of Moore’s Law, interconnects are also becoming the industry’s choke point.
Book repository "Analysis and Design of Elementary MOS Amplifier Stages" - bmurmann/Book-on-MOS-stages
List of awesome open source hardware tools, generators, and reusable designs - aolofsson/awesome-opensource-hardware
A technical paper titled “Beware of Discarding Used SRAMs: Information is Stored Permanently” was published by researchers at Auburn University. The paper won “Best Paper Award” at the IEEE International Conference on Physical Assurance and Inspection of Electronics (PAINE) Oct…
The next of a series of primers in semicap manufacturing.
Gallium arsenide (GaAs) technology is a type of semiconductor material used in the manufacturing of various electronic devices. It is known for its high electron mobility, which allows it to operate at higher speeds and with lower power consumption compared to other…
Conventional wisdom says that trying to attach system memory to the PCI-Express bus is a bad idea if you care at all about latency. The further the memory
A new technical review paper titled “Carbon nanotube transistors: Making electronics from molecules” was published by researchers at Duke University, Northwestern University, and Stanford University. “Between the opportunities in high-performance digital logic with the potential…
Why and when it's needed, and what tools and technologies are required.
The world's largest chip scales to new heights.
Eliyan is emerging from stealth mode, unveiling the successful tapeout of its high-performance UCIe-compliant die-to-die interconnect technology in 5 nm process.