Backside Power Delivery (BSPD), also called Backside Power Delivery Network (BSPDN) or backside power via (BPV) technology, is a semiconductor manufacturing innovation in which the chip’s primary power distribution network … Continue reading "Backside Power Delivery (BSPD) Wiki"
A new technical paper titled “Energy-Accuracy Trade-Offs in Massive MIMO Signal Detection Using SRAM-Based In-Memory Computing” was published by researchers at the University of Illinois at Urbana–Champaign. Abstract “This paper investigates the use of SRAM-based in-memory…
Note: “This paper investigates the use of SRAM-based in-memory computing (IMC) architectures for designing energy efficient and accurate signal detectors for massive multi-input multi-output (MIMO) systems. SRAM-based IMCs are the state-of-the-art for executing deep learning workloads in terms of energy efficiency and compute density. However, given the more stringent accuracy requirements of massive…
Materials breakthroughs and process innovations are unlocking next-gen chip scaling, with Southeast Asia playing a pivotal role in semiconductor evolution. By Andrew Goh, Corporate Vice President and General Manager, Southeast Asia at Lam Research
Tungsten, long used for interconnects due to its robustness and thermal stability, is now reaching critical scaling and performance bottlenecks. Its relatively high resistivity and poor conformality in narrow, high-aspect-ratio features
he industry is turning to molybdenum (Mo) as a breakthrough alternative. Mo offers lower resistivity, enabling faster electron flow and reduced power consumption, which are crucial for maintaining performance at smaller nodes. Its ability to be deposited without a barrier layer simplifies…
Traditional von Neumann architectures suffer from fundamental bottlenecks due to continuous data movement between memory and processing units, a challenge that worsens with technology scaling as electrical interconnect delays become more significant. These limitations impede the…
Researchers are testing a special coating on GaN devices that may enhance transistor performance by breaking the Schottky limit.
A 94-page research report on interconnect fundamentals for semiconductor engineers.
Table of Contents Motivation Optimization goal of GPUs Key concepts of GPUs - software and...
28 fabs later
Thin lines and limited ground planes keep RDL interconnects short.
Finding defects now requires multiple data types, and a much more thorough search.
Glass cloth maker Nittobo is latest example country's overlooked role in supply chain
This review compares wafer-scale AI accelerators and single-chip GPUs in terms of performance, energy efficiency, and cost for high-performance AI applications. It highlights enabling technologies, such as CoWoS, and explores future directions including 3D integration, photonic…
A slide deck revealing the plans (and expectations) for next-generation High Bandwidth Memory (HBM) technology was published by Korea Advanced Institute of Science and Technology and TERA (Terabyte Interconnection and Package Laboratory). Starting with HBM4. This will be the…
The IP industry is no stranger to boom and bust cycles, and it looks to be at the crest of another wave.
An in-depth look at semiconductor processing equipment: considerations, selection, operation, and supporting info. …
For the last several decades, one avenue of technological progress has towered over nearly everything else: semiconductors.
Thermodynamic computing isn't just a rebrand of probabilistic computing
Normal Computing’s prototype chip, which they termed the stochastic processing unit (SPU), consists of eight capacitor-inductor resonators and random noise generators. Each resonator is connected to each other resonator via a tunable coupler. The resonators are initialized with randomly generated…
An adaptive metal fill extraction technique dynamically adjusts the level of detail based on the design context, such as the density of...
CXL 3.1 and PCIe 6.2 are transforming AI with improved data transfer and memory pooling.
Many features of UCIe 2.0 seen as “heavy” are optional, causing confusion.
The spec is defined with so many variants that you can tailor it to your exact needs. It’s applicable for everything from automotive to high-performance compute to AI to mil/aero because it has so many flavors. That’s also a curse to an IP provider. How do you support all those flavors?”
the latter predominates, since virtually all projects underway are internal projects, with all chiplets being internally created and applied. Interoperability with externally sourced chiplets is therefore not a concern
Silicon is the industry standard for semiconductors. However, GaN has become a more beneficial option for RF applications.
TSMC also revealed developments in advanced packaging technologies at the NA Technology Symposium, and they look interesting.
Unpacking the bear thesis on power semis and TSMC’s footnote in the story
The BSIM (Berkeley Short-channel IGFET Model) Group, located in the Department of Electrical Engineering and Computer Sciences (EECS) at the University of California, Berkeley, develops physics-based, accurate, scalable, robust, and predictive MOSFET SPICE models for circuit…
Huawei patented a new technology called "ternary logic" that can develop energy-efficient AI chips. The new patent confirms the company's effo
Most people think of machine instructions as the fundamental steps that a computer performs. However, many processors have another layer of ...
China’s biggest semiconductor manufacturer, SMIC, is rumored to complete 5nm chip development in 2025, leading to advanced chip orders from Huawei
Number of designs that are late increases. Rapidly rising complexity is the leading cause, but tools, training, and workflows need to improve.
“Historically, it’s been around 30%. Two years ago it dropped to 24% from 2023 to 2024. It dropped to 14% this time around. That’s one data point. Another is that historically we’ve seen about two-thirds of projects were behind schedule. That increased to 75% behind schedule.”
The Future of AI Accelerators: A Roadmap of Industry Leaders The AI hardware race is heating up, with major players like NVIDIA, AMD, Intel, Google, Amazon, and more unveiling their upcoming AI accelerators. Here’s a quick breakdown of the latest trends: Key Takeaways: NVIDIA…
Nvidia's endorsement of co-packaged optics means the time is right
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BintangChip is one of the world’s leading specialty foundry groups for analog/mixed-signal semiconductor technologies. As a pure-play foundry, we provide manufacturing and strong design support services to our customers that design analog/mixed-signal integrated circuits and…
It is often said that companies – particularly large companies with enormous IT budgets – do not buy products, they buy roadmaps. No one wants to go to
Pixel-level dose correction improves the quality of masks written by multi-beam.
Getting 'low level' with Nvidia and AMD GPUs
Novel combinations show promise for different applications.
[vc_row][vc_column column_width_percent=”90″ gutter_size=”3″ overlay_alpha=”50″ shift_x=”0″ shift_y=”0″ shift_y_down=”0″ z_index=”0″ medium_width=”0″ mobile_width=”0″ width=”1/1″ uncode_shortcode_id=”158708″][vc_column_text uncode_shortcode_id=”154284″] Conventional wisdom in…
After persistent rumors refused to recede, AMD steps in with a clear explanation why dual-CCD V-Cache doesn't exist.
No, the actual reason AMD won't make a dual-V-Cache chip is much simpler: it would be pointless and a waste of money.
Introduction to Gate-All-Around (GAA) Transistors Gate-all-around (GAA) transistors are a newly introduced type of transistor structure: the gate terminal connects with the channel on all sides. Gate-All-Around transistors are a multi-gate field effect transistors type where a…
In 1993, Intel released the high-performance Pentium processor, the start of the long-running Pentium line. The Pentium had many improvement...
The CCD stack with 3D V-Cache on the AMD Ryzen 7 9800X3D is only 40-45µm in total, but the rest of the layers add up to a whopping 750µm.
stability
9800X3D brought the 3D chiplet underneath the CC
Large Language Models (LLMs) have become a cornerstone of artificial intelligence, driving advancements in natural language processing and decision-making tasks. However, their extensive power demands, resulting from high computational overhead and frequent external memory…
And Intel shows how far these devices could go
It hasn’t achieved commercial success, but there is still plenty of development happening; analog IMC is getting a second chance.
China has announced the development of its latest quantum system, combining the Xiaohong-504, a 504-qubit superconducting quantum chip, with the Tianyan-504 quantum computer. The breakthrough comes from China Telecom Quantum Group (CTQG), which will use the new supercomputer to…
There is no shortage of top-name – and even lesser known – companies pursuing the white whale of developing a quantum computer that can run workloads and
A new technical paper titled “Hardware Security Failure Scenarios: Potential Hardware Weaknesses” was published by NIST. Abstract “Hardware is often assumed to be robust from a security perspective. However, chips are both created with software and contain complex encodings…
The manipulation of mechanical strain in materials, also known as strain engineering, has allowed engineers to advance electronics over the past decades, for instance enhancing the mobility of charge ...
A loop buffer sits at a CPU's frontend, where it holds a small number of previously fetched instructions.
Joining the ASML Lego Collection - the TWINSCAN EXE:5000. The latest addition to you ASML Lego collection has arrived. Rick Lenssen from D&E (designer of the Lego ASML Skyline and the Lego TWINSCAN NXE:3400C) has delivered another masterpiece in technology, once again made…