RF Engineering is Black Magic
Tribal knowledge of RF design, EV range vs. temperature on the dyno, OpenAI's expanding robotic division, and more.
semiconductors
Intel’s 18A-P Goes Beyond a 9% Speed Bump, Adding 50% Better Thermal Conductivity and Tighter Skew Corners to Win Foundry Customers
As Intel primes its 18A-P technology at external customers, the company is sharing new insights into its enhanced performance & features.
How to Overcome the Advanced Node Physical Verification...
This blog looks at the details of how Synopsys IC Validator can overcome the advanced node physical verification bottleneck.
TSMC Technology Symposium 2026 Overview - SemiWiki
TSMC revenue is expected by me to grow 30-40%. Here is the hitch: While wafer pricing is stable chip pricing is not.
#semiconductors #dram #memory #ai #artificialintelligence #cloud #cloudcomputing #datacenters #hbm #highbandwidthmemory #automotive #adas…
DRAM Market Shift: From Mobile to Infrastructure (2023–2030) The latest DRAM demand outlook highlights a clear structural transition: memory demand is moving from mobile-driven to infrastructure-driven growth. 1. Infrastructure Becomes Dominant Servers & Workstations grow from…
#ddr4 #lpddr4 #ddr5 #lpddr5x #semiconductors #memoryindustry #supplychain #automotivetech #industrialiot #ai #techstrategy #eol | Nick…
🚨 DDR4 / LPDDR4: The Beginning of the End — or a Strategic Reset? The memory industry is approaching a pivotal inflection point—and the signals are becoming impossible to ignore. Recent developments from Samsung indicate that legacy nodes such as LPDDR4 (and increasingly DDR4)…
Rambus Quietly Builds The Missing Piece Of AI Servers As SOCAMM2 Becomes The Favorite AI Memory Standard
Rambus has announced its LPDDR5X SOCAMM2 memory chipset, a vital component to enable the next-gen compact memory for AI datacenters.
Tenstorrent’s Optimized AI Model, Running on Blackhole Servers, Generates 5-Sec Video In Just 2.4 Seconds
Tenstorrent has previewed its optimized AI model, which is powered by the Blackhole servers, offering blazing-fast video generation speeds.
Panel-Level Packaging's Second Wave Meets Engineering Reality
The cost case is strengthening, but glass, warpage, and bonding yield stand in the way.
Google Splits TPUv8 Strategy Into Two Chips, Handing Broadcom Training and MediaTek Inference Duties
Google is preparing two brand new chips under its TPUv8 belt, one for training & one for inference AI workloads.
AMD 3D V-Cache Turns Ryzen Into a Surprise RAG AI Weapon, With An 88% Boost Over Non-X3D CPUs
AMD's 3D V-Cache CPUs deliver a huge boost versus the Non-X3D part in AI benchmarks, showcasing why they are best suited for RAG pipelines.
But LLMs' limitations can be seen when it needs to generate responses on data it wasn't trained on.
That's where RAG or Retrieval-Augmented Generation) comes into play
The Bromine Chokepoint: How Strife in the Middle East Could Halt Production of the World’s Memory Chips
The U.S.-Israeli war with Iran, now in an unstable ceasefire, has exposed a structural failure in the global semiconductor memory supply chain, and it is
Reinventing Embedded Memory: Solving The SRAM Scaling Wall
A new embedded memory architecture with a three-transistor cell.
Lumotive Debuts ‘World’s First 2D Photonic Beamforming Chip’
The startup's programmable chip uses a metasurface architecture to control light without moving parts.
Inside the TSMC Patent: How Himax Quietly Became a Key Link in the...
Himax Technologies has long been seen as a peripheral player in the AI boom. But that perception may be about to change. Buried inside a series of recent TSMC patent filings lies an unexpected...
Microsoft-backed startup raises $40 million for advanced chipmaking equipment tech
Lace, a Norway-headquartered chipmaking equipment startup which is backed by Microsoft, has raised $40 million in funding to further develop a technology that could enable significant advances in semiconductor design and manufacturing, the company said on Monday.
Anthropic's Compute Advantage: Why Silicon Strategy is Becoming an AI Moat
Why Anthropic’s integration into hyperscaler silicon programs may give it a lasting advantage in the economics of frontier AI.
An exclusive tour of Amazon’s Trainium lab, the chip that’s won over Anthropic, OpenAI, even Apple
Shortly after Amazon announced its $50 billion investment in OpenAI, AWS invited me on a private tour of the chip lab at the heart of the deal.
Note: Based on the article **[An exclusive tour of Amazon’s Trainium lab, the chip that’s won over Anthropic, OpenAI, even Apple](#rid:1653401870)**, here are the key points: ### Strategic Impact & Partnerships * **Major Adoption:** Amazon’s custom chips have secured massive commitments from leading AI labs. **Anthropic** runs Claude on over 1 million Trainium2 chips, and **OpenAI** recently signed a…
The Great AI Silicon Shortage
TSMC N3 Wafer Shortages, Memory Constraints, Datacenter Bottlenecks, Supply Chain Wars Winner
Designing AI Chip Software and Hardware
Designing AI Chip Hardware and Software Bjarke Hammersholt Roune 2026 This document is, for now, open for comments. You can use the Google Docs comment feature to add comments anywhere. Thanks! What is this document? I was going to start an AI chip company and this document…
Space Forge Evaluates In-Orbit Manufacturing Tech
Space Forge's orbital furnace could redefine semiconductor production with space-grown crystals.
A Deep Dive Into Modern Computer Memory: ROM, DRAM, SRAM & Flash
Explore the four key modern memory types: ROM, DRAM, SRAM, and flash, their unique roles, and trade-offs in speed, cost, and storage.
Bulk RRAM: Scaling the AI Memory Wall
UC San Diego researchers have reimagined RRAM, creating a device that could redefine AI's memory challenges. Discover how this could impact edge computing.
Gate-All-Around (GAA) Technology for Sustainable AI - SemiWiki
Key takeaways ▼ The transition from FinFET to Gate-All-Around (GAA) transistor technology represents a pivotal moment in the evolution of logic devices, driven by both physical scaling limits and the … Continue reading "Gate-All-Around (GAA) Technology for Sustainable AI"
Engineering Challenges Grow With Crystalline Defects
Tighter process control and yield optimization still cannot mitigate crystalline defects.
Understanding the PDK Generation Process - Technical Articles
In this article, we'll walk through the steps of generating a Process Design Kit (PDK) for digital standard cell libraries.
Breakthrough Metal Could Revolutionize Chip Cooling And Thermal Management
A multi-institution research team has discovered a metallic material that conducts heat nearly three times more efficiently than copper or silver.
1,000 CFETs, SK Hynix Next-Gen NAND, Interconnects Beyond Copper, 2D Materials, and More
IEDM 2025 Round-Up
For leading fabs, this is a 3xx-layer 3D NAND process, which yields on the order of 20-30 Gb/mm2 of memory.
321-layer process has 44% more memory per wafer than the previous generation 238-layer technology
NVIDIA Rubin Is The Most Advanced AI Platform On The Planet: Up To 50 PFLOPs With HBM4, Vera CPU With 88 Olympus Cores, And Delivers 5x…
NVIDIA is formally announcing its Rubin AI platform today which will be the heart of next-gen Data Centers, with a 5x upgrade over Blackwell.
'It's amazing' – the wonder material very few can make
Just a handful of companies can make cadmium zinc telluride, a material with powerful properties.
FPGAs Need a New Future
FPGAs are limited by outdated proprietary software. Learn how embracing open-source tools is necessary to modernize FPGA development and unlock their full potential.
The Accounting Uproar Over How Fast an AI Chip Depreciates - Slashdot
Tech giants including Meta, Alphabet, Microsoft and Amazon have all extended the estimated useful lives of their servers and AI equipment over the past five years, sparking a debate among investors about whether these accounting changes are artificially inflating profits. Meta…
High Bandwidth Flash is years away
Rubber CMOS Brings Stretchable ‘Sensory Skin’ Closer to Reality
A new “rubbery CMOS” platform combines fully stretchable p- and n-type transistors, enabling skin-like logic circuits and a tactile “sensory skin” for wearables, implants, and soft robotics.
Unusual circuits in the Intel 386's standard cell logic
I've been studying the standard cell circuitry in the Intel 386 processor recently. The 386, introduced in 1985, was Intel's most complex pr...
The Thermal Trap: How Dielectrics Limit Device Performance
Thin films for insulating different components are causing dissipation issues in advanced chips.
Solving the QLC NAND Flash SSD Scaling Challenge - Industry Articles
Learn how to solve QLC NAND's endurance, ECC, and performance issues for hyperscale. The approach blends a PCIe Gen5 controller with hardware-accelerated LDPC, PerformaShape QoS, and more.
Why In-Memory Computation Is So Important For Edge AI
Researchers focus on limiting data movement to reduce power and latency in edge devices.
Charting The Frontiers Of Photomask Technology And Extreme Ultraviolet Lithography
Modeling, simulation, and digital twins enable EUV innovation.
The vertical GaN transistor: Time for take-off - Compound Semiconductor News
Our selection of industry specific magazines cover a large range of topics.
iKlips S: Thumb-Sized Fingerprint SSD That Moves 1GB in 3 Seconds – Yanko Design
Interconnect Innovations In High Bandwidth Memory: Part 2
Bump technologies are being pushed beyond what was thought to be their physical and performance limits.
Beyond Von Neumann: Toward a unified deterministic architecture
The mechanism behind this is a time-resource matrix: A scheduling framework that orchestrates compute, memory and control resources across time. Much like a train timetable, scalar, vector and matrix operations move across a synchronized compute fabric without pipeline stalls or contention.
By predicting exactly when data will arrive — whether in 10 cycles or 200 — Deterministic Execution can slot dependent instructions into the right future cycle. This turns latency from a hazard into a schedulable event, keeping the execution units fully utilized and avoiding the massive thread and…
Where Are Semiconductor Fabs Currently Being Built Around the World? - Z2Data
The semiconductor manufacturing landscape continues to grow, with new fabs and expansions to current production sites taking place in the U.S., Asia, and other key manufacturing regions.
The power GaN race: market growth, consolidation, and new entrants
The expanding role of GaN in power electronics. Gallium nitride (GaN) has emerged as one of the most disruptive semiconductor technologies of the decade, with a market projected to reach $3 billion by 2030. Consumer applications, particularly fast chargers, have been the early…
The Demise Of Static Timing Verification?
Timing is increasingly dependent on vectors. Can static techniques continue to deliver the necessary results? Maybe.
The Future of Memory: Limits and Opportunities
Memory latency, bandwidth, capacity, and energy increasingly limit performance. In this paper, we reconsider proposed system architectures that consist of huge (many-terabyte to petabyte scale) memories shared among large numbers of CPUs. We argue two practical engineering…
Backside Power Delivery (BSPD) Wiki
Backside Power Delivery (BSPD), also called Backside Power Delivery Network (BSPDN) or backside power via (BPV) technology, is a semiconductor manufacturing innovation in which the chip’s primary power distribution network … Continue reading "Backside Power Delivery (BSPD) Wiki"
Energy-Efficient Signal Detectors For Massive MIMO Using SRAM-Based IMCs
A new technical paper titled “Energy-Accuracy Trade-Offs in Massive MIMO Signal Detection Using SRAM-Based In-Memory Computing” was published by researchers at the University of Illinois at Urbana–Champaign. Abstract “This paper investigates the use of SRAM-based in-memory…
Note: “This paper investigates the use of SRAM-based in-memory computing (IMC) architectures for designing energy efficient and accurate signal detectors for massive multi-input multi-output (MIMO) systems. SRAM-based IMCs are the state-of-the-art for executing deep learning workloads in terms of energy efficiency and compute density. However, given the more stringent accuracy requirements of massive…
Materials and Process Innovation Enable Scaling of Next-Generation Chips
Materials breakthroughs and process innovations are unlocking next-gen chip scaling, with Southeast Asia playing a pivotal role in semiconductor evolution. By Andrew Goh, Corporate Vice President and General Manager, Southeast Asia at Lam Research
Tungsten, long used for interconnects due to its robustness and thermal stability, is now reaching critical scaling and performance bottlenecks. Its relatively high resistivity and poor conformality in narrow, high-aspect-ratio features
he industry is turning to molybdenum (Mo) as a breakthrough alternative. Mo offers lower resistivity, enabling faster electron flow and reduced power consumption, which are crucial for maintaining performance at smaller nodes. Its ability to be deposited without a barrier layer simplifies…