Trillium: Google’s TPU Powerhouse Behind Its New AI Models
Google's sixth-generation tensor processing unit (TPU) stole the company's I/O developer conference stage with its higher-than-ever computing performance.
semiconductors
JEDEC Confirms CAMM2 Memory For Desktop PCs: DDR6 Up To 17.6 Gbps & LPDDR6
DDR6 & LPDDR6 memory will feature super-fast speeds of up to 17.6 Gbps while the CAMM2 DRAM standard is headed to desktops.
TSMC to Expand CoWoS Capacity by 60% Yearly Through 2026
Competitive Open-Source EDA Tools
A technical paper titled “Basilisk: Achieving Competitive Performance with Open EDA Tools on an Open-Source Linux-Capable RISC-V SoC” was published by researchers at ETH Zurich and University of Bologna. Abstract: “We introduce Basilisk, an optimized application-specific…
How to Put a Data Center in a Shoebox
Imec’s plan to use superconductors to shrink computers
One Cerebras Wafer Beats An Exascale Super At Molecular Dynamics
We think that waferscale computing is an interesting and even an inevitable concept for certain kinds of compute and memory. But inevitably, the work you
Wafer Dicing: Ultimate Guide
Wafer dicing is a critical process within the semiconductor manufacturing. It’s the step where silicon dies are separated from each other. Semiconductor wafer dicing techniques have evolved over time, from traditional blade dicing to more advanced methods such as laser and…
AI memory emerges as new battleground for SK Hynix, Samsung and others
Demand for high-bandwidth memory is driving competition -- and prices -- higher
AI chip startup Deepx raises $80m, receives $529m valuation
Funding round was led by SkyLake Equity Partners
A Look At Intel 4 Process Technology
A look at Intel's next-generation high-performance process technology, Intel 4.
TSMC Jumps Into Silicon Photonics, Lays Out Roadmap For 12.8 Tbps COUPE On-
Intel’s 14A Magic Bullet: Directed Self-Assembly (DSA)
How High-NA EUV can be economically viable at the 1.4nm process node
Rambus Unveils GDDR7 Memory Controller IP: PAM3 Signaling, Up To 48 Gbps Da
Rambus has unveiled its next-gen GDDR7 memory controller IP, featuring PAM3 Signaling, and up to 48 Gbps transfer speeds.
Exploring Process Scenarios To Improve DRAM Device Performance
On the use and benefits of virtual fabrication in the development of DRAM saddle fin profiles
Biden has brought the ban hammer down on US export of AI chips to China
Datacenter GPUs and some consumer cards now exceed performance limits
Intel preps export-friendly lower-power Gaudi 3 AI chips made for China
Beijing will be thrilled by this nerfed silicon
Nvidia Blackwell Perf TCO Analysis - B100 vs B200 vs GB200NVL72
GPT-4 Profitability, Cost, Inference Simulator, Parallelism Explained, Performance TCO Modeling In Large & Small Model Inference and Training
Google just released its AI chip rival to Nvidia
Google’s new AI chip is a rival to Nvidia, and its Arm-based CPU will compete with Microsoft and Amazon
How To Build A Better “Blackwell” GPU Than Nvidia Did
While a lot of people focus on the floating point and integer processing architectures of various kinds of compute engines, we are spending more and more
4 Fiber Optic Networking Spotlights From the Optical Fiber Conference
Some of the leaders of the networking industry showed up to the Optical Fiber Conference, including Broadcom, MediaTek, Semtech, and MaxLinear.
The Challenges Of Working With Photonics
From curvilinear designs to thermal vulnerabilities, what engineers need to know about the advantages and disadvantages of photonics.
Half of Russian-Made Chips Are Defective
Anton Shilov reports via Tom's Hardware: About half of the processors packaged in Russia are defective. This has prompted Baikal Electronics, a Russian processor developer, to expand the number of packaging partners in the country, according to a report in Vedomosti, a…
Lenovo Shows Huge Optimism Towards AMD’s Instinct MI300X AI Accelerators
Lenovo, the firm emerging as a driving force behind AI computing, has expressed tremendous optimism about AMD's Instinct MI300X accelerator.
The world's semiconductor industry hinges on a single quartz factory in Nor
The deposits formed 380 million years ago when Africa collided with North America.
Silicon carbide substrate costs falling as larger diameters adopted
Number of 8-inch SiC fabs under construction or planned globally reaches 11
Accelerator Industry Model
The SemiAnalysis AI accelerator model is used to gauge historical and future accelerator production by company and type.
DRAM Chips Perform Functionally-Complete Boolean Operations (ETH Zurich)
A new technical paper titled “Functionally-Complete Boolean Logic in Real DRAM Chips: Experimental Characterization and Analysis” was published by researchers at ETH Zurich. Abstract: “Processing-using-DRAM (PuD) is an emerging paradigm that leverages the analog operational…
Synopsys Shepards Circuits Towards 1.6T Ethernet
The Ethernet roadmap has had a few bumps and potholes in the four and a half decades since the 10M generation was first published in 1980. Remember the
How To Stop Row Hammer
What it is, and why this has become such a significant security issue.
Techniques To Identify And Correct Asymmetric Wafer Map Defects Caused By D
We explore the causes and implications of asymmetric wafer defects in semiconductor manufacturing. We also consider the use of virtual process modeling to understand and mitigate these structural failures.
Authority.Integrity. Accuracy.
After coming up against the limits of physics, scientists are rethinking chip architecture like never before
ASAP5: A predictive PDK for the 5 nm node
We present a predictive process design kit (PDK) for the 5 nm technology node, the ASAP5 PDK. ASAP5 is not related to a particular foundry and the ass…
Grokking Groq’s Groqness
Startup Groq has developed an machine learning processor that it claims blows GPUs away in large language model workloads – 10x faster than an Nvidia GPU at 10 percent of the cost, and needing a tenth of the electricity. Update: Groq model compilation time and time from access…
Groq Inference Tokenomics: Speed, But At What Cost?
Faster than Nvidia? Dissecting the economics
The Seven Pillars Of IC Package Physical Design
Embracing emerging approaches is essential for crafting packages that address the evolving demands of sustainability, technology, and consumer preferences.
Application Specific Lithography: Avoiding Stochastic Defects and Image Imb
The discussion of any particular lithographic application often refers to…
Nvidia’s Big Tech Rivals Put Their Own A.I. Chips on the Table - The New Yo
Chafing at their dependence, Amazon, Google, Meta and Microsoft are racing to cut into Nvidia’s dominant share of the market.
The New, New Transistor
In power electronics, aluminum nitride could overtake two powerhouses that only recently bested silicon
Micron NVDRAM may never become a product
Micron’s NVDRAM chip could be a proving ground for technologies used in other products – and not become a standalone product itself. The 32Gb storage-class nonvolatile random-access memory chip design was revealed in a Micron paper at the December IEDM event, and is based on…
Choosing the Best Wide Bandgap Technology for Your Application - Industry Articles
Understanding the unique advantages provided by silicon carbide (SiC) and gallium nitride (GaN) can help you select the optimal technology to meet your products’ power, thermal, and size requirements.
Wafer Wars: Deciphering Latest Restrictions On AI And Semiconductor Manufacturing
China's Countermove: How Beijing is Dodging New Semiconductor Restrictions
Samsung Unveils Shinebolt HBM3E Memory At Nearly 10Gbps And Blistering 32Gb
We're getting a first glimpses of Samsung's next-generation HBM3E and GDDR7 memory chips.
A Comprehensive RF Characterization and Modeling Methodology for the 5nm Te
This paper aims to provide insights into the thermal, analog, and RF attributes, as well as a novel modeling methodology, for the FinFET at the industry standard 5nm CMOS technology node. Thermal characterization shows that for a 165K change in temperature, the Sub-threshold…
The Ultimate Signoff (TapeOut) Checklist
In semiconductor design, “sign-off” during the tape-out (tapeout) of a chip refers to the formal approval process to ensure that the chip design is error-free, meets all specifications, and is ready for manufacturing at the foundry. It is essential because it minimizes the risk…
VLSI Physical Design
Intel unveils glass substrates for chips to advance Moore’s Law
Join our daily and weekly newsletters for the latest updates and exclusive content on industry-leading AI coverage. Learn More Intel said it has made a significant breakthrough in the development of glass substrates for next-generation advanced packaging in an attempt to stay on…
ASML to Deliver First High-NA EUV Tool This Year
Criteria & Assumptions — SkyWater SKY130 PDK 0.0.0-356-g49d3c73 documentati
“Downfall” bug affects years of Intel CPUs, can leak encryption keys and mo
Researchers also disclosed a separate bug called “Inception” for newer AMD CPUs.
Downfall Attacks
Downfall attacks targets a critical weakness found in billions of modern processors used in personal and cloud computers.